diff options
| author | Keith Packard <keithp@keithp.com> | 2018-09-11 01:28:03 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2018-10-13 08:22:50 -0700 |
| commit | f7ca88282466c271bad5e25e804729580fe83c47 (patch) | |
| tree | 169d841680f804803b20621afa831ec2320c4ce0 /src/stm32f4/stm32f4.h | |
| parent | 621d1529d6bc07a3f4bd27fb2d02d5b3161a3a6a (diff) | |
altos/stm32f4: Fix clock configuration
Was running the PLL input too slow (it wants 2MHz).
Was configuring the PLL_P factor wrong (needs magic values, not P
value)
Set up clock debugging for PA8 and PC9 output. Enable on disco board
for debugging.
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'src/stm32f4/stm32f4.h')
| -rw-r--r-- | src/stm32f4/stm32f4.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/stm32f4/stm32f4.h b/src/stm32f4/stm32f4.h index a351f086..3429e458 100644 --- a/src/stm32f4/stm32f4.h +++ b/src/stm32f4/stm32f4.h @@ -125,6 +125,10 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_PLLCFGR_PLLN 6 #define STM_RCC_PLLCFGR_PLLN_MASK 0x1ff #define STM_RCC_PLLCFGR_PLLP 16 +#define STM_RCC_PLLCFGR_PLLP_DIV_2 0 +#define STM_RCC_PLLCFGR_PLLP_DIV_4 1 +#define STM_RCC_PLLCFGR_PLLP_DIV_6 2 +#define STM_RCC_PLLCFGR_PLLP_DIV_8 3 #define STM_RCC_PLLCFGR_PLLP_MASK 0x3 #define STM_RCC_PLLCFGR_PLLSRC 22 #define STM_RCC_PLLCFGR_PLLSRC_HSI 0 |