From f7ca88282466c271bad5e25e804729580fe83c47 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 11 Sep 2018 01:28:03 -0700 Subject: altos/stm32f4: Fix clock configuration Was running the PLL input too slow (it wants 2MHz). Was configuring the PLL_P factor wrong (needs magic values, not P value) Set up clock debugging for PA8 and PC9 output. Enable on disco board for debugging. Signed-off-by: Keith Packard --- src/stm32f4/stm32f4.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/stm32f4/stm32f4.h') diff --git a/src/stm32f4/stm32f4.h b/src/stm32f4/stm32f4.h index a351f086..3429e458 100644 --- a/src/stm32f4/stm32f4.h +++ b/src/stm32f4/stm32f4.h @@ -125,6 +125,10 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_PLLCFGR_PLLN 6 #define STM_RCC_PLLCFGR_PLLN_MASK 0x1ff #define STM_RCC_PLLCFGR_PLLP 16 +#define STM_RCC_PLLCFGR_PLLP_DIV_2 0 +#define STM_RCC_PLLCFGR_PLLP_DIV_4 1 +#define STM_RCC_PLLCFGR_PLLP_DIV_6 2 +#define STM_RCC_PLLCFGR_PLLP_DIV_8 3 #define STM_RCC_PLLCFGR_PLLP_MASK 0x3 #define STM_RCC_PLLCFGR_PLLSRC 22 #define STM_RCC_PLLCFGR_PLLSRC_HSI 0 -- cgit v1.2.3