diff options
| author | Keith Packard <keithp@keithp.com> | 2019-04-21 16:49:19 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2019-04-21 16:54:54 -0700 |
| commit | 5d3436ed8551537287dc6cf418f93b0989e1aee8 (patch) | |
| tree | cb940eabcc3f4a1cb35ab1e35cd6e7b32272e974 /src/stm/stm32l.h | |
| parent | 49ce3e9a2eb4e1918773b80c355d720a3dadc7e0 (diff) | |
altos: get ao_max6691 driver working
The driver uses a timer connected to a DMA engine to measure pulse
widths from the chip. We get 11 pulses for 4 channels; the first pulse
is caused by the timer starting up, the next two are the marker pulse
and then 8 more indicating the end of the high and low periods for
each channel.
The driver API returns the 8 pulse widths; the caller is expected to
know what to do with those values as using them requires knowing the
value of the configuration resistor and the characteristics of the
thermistors.
The test code assumes a 1k configuration resistor, using that it computes
the resistance of the four thermistors.
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'src/stm/stm32l.h')
| -rw-r--r-- | src/stm/stm32l.h | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h index 5741a846..310b334b 100644 --- a/src/stm/stm32l.h +++ b/src/stm/stm32l.h @@ -1871,6 +1871,51 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3 #define STM_TIM234_CCMR1_CC1S_MASK 3 +#define STM_TIM234_CCMR1_IC2F 12 +#define STM_TIM234_CCMR1_IC2F_NONE 0 +#define STM_TIM234_CCMR1_IC2F_CK_INT_N_2 1 +#define STM_TIM234_CCMR1_IC2F_CK_INT_N_4 2 +#define STM_TIM234_CCMR1_IC2F_CK_INT_N_8 3 +#define STM_TIM234_CCMR1_IC2F_DTS_2_N_6 4 +#define STM_TIM234_CCMR1_IC2F_DTS_2_N_8 5 +#define STM_TIM234_CCMR1_IC2F_DTS_4_N_6 6 +#define STM_TIM234_CCMR1_IC2F_DTS_4_N_8 7 +#define STM_TIM234_CCMR1_IC2F_DTS_8_N_6 8 +#define STM_TIM234_CCMR1_IC2F_DTS_8_N_8 9 +#define STM_TIM234_CCMR1_IC2F_DTS_16_N_5 10 +#define STM_TIM234_CCMR1_IC2F_DTS_16_N_6 11 +#define STM_TIM234_CCMR1_IC2F_DTS_16_N_8 12 +#define STM_TIM234_CCMR1_IC2F_DTS_32_N_5 13 +#define STM_TIM234_CCMR1_IC2F_DTS_32_N_6 14 +#define STM_TIM234_CCMR1_IC2F_DTS_32_N_8 15 +#define STM_TIM234_CCMR1_IC2PSC 10 +#define STM_TIM234_CCMR1_IC2PSC_NONE 0 +#define STM_TIM234_CCMR1_IC2PSC_2 1 +#define STM_TIM234_CCMR1_IC2PSC_4 2 +#define STM_TIM234_CCMR1_IC2PSC_8 3 +#define STM_TIM234_CCMR1_IC1F 4 +#define STM_TIM234_CCMR1_IC1F_NONE 0 +#define STM_TIM234_CCMR1_IC1F_CK_INT_N_2 1 +#define STM_TIM234_CCMR1_IC1F_CK_INT_N_4 2 +#define STM_TIM234_CCMR1_IC1F_CK_INT_N_8 3 +#define STM_TIM234_CCMR1_IC1F_DTS_2_N_6 4 +#define STM_TIM234_CCMR1_IC1F_DTS_2_N_8 5 +#define STM_TIM234_CCMR1_IC1F_DTS_4_N_6 6 +#define STM_TIM234_CCMR1_IC1F_DTS_4_N_8 7 +#define STM_TIM234_CCMR1_IC1F_DTS_8_N_6 8 +#define STM_TIM234_CCMR1_IC1F_DTS_8_N_8 9 +#define STM_TIM234_CCMR1_IC1F_DTS_16_N_5 10 +#define STM_TIM234_CCMR1_IC1F_DTS_16_N_6 11 +#define STM_TIM234_CCMR1_IC1F_DTS_16_N_8 12 +#define STM_TIM234_CCMR1_IC1F_DTS_32_N_5 13 +#define STM_TIM234_CCMR1_IC1F_DTS_32_N_6 14 +#define STM_TIM234_CCMR1_IC1F_DTS_32_N_8 15 +#define STM_TIM234_CCMR1_IC1PSC 2 +#define STM_TIM234_CCMR1_IC1PSC_NONE 0 +#define STM_TIM234_CCMR1_IC1PSC_2 1 +#define STM_TIM234_CCMR1_IC1PSC_4 2 +#define STM_TIM234_CCMR1_IC1PSC_8 3 + #define STM_TIM234_CCMR2_OC4CE 15 #define STM_TIM234_CCMR2_OC4M 12 #define STM_TIM234_CCMR2_OC4M_FROZEN 0 |