diff options
| author | Bdale Garbee <bdale@gag.com> | 2017-12-05 13:23:09 -0700 |
|---|---|---|
| committer | Bdale Garbee <bdale@gag.com> | 2017-12-05 13:23:09 -0700 |
| commit | 2f8fce1cf6ce4bd12a836cc8ee15f4edbc95c95e (patch) | |
| tree | 19a1bcb93694eb259f29e9ef9690bb31a9b8fa60 /src/drivers/ao_mpu9250.h | |
| parent | d314a5654fafa5eac86d8293f1197a2f2c2eac72 (diff) | |
| parent | 185b11367cd85948885fceafb5d46303b6f1356d (diff) | |
Merge branch 'master' of ssh://git.gag.com/scm/git/fw/altos
Diffstat (limited to 'src/drivers/ao_mpu9250.h')
| -rw-r--r-- | src/drivers/ao_mpu9250.h | 71 |
1 files changed, 60 insertions, 11 deletions
diff --git a/src/drivers/ao_mpu9250.h b/src/drivers/ao_mpu9250.h index a124d799..df1be7c7 100644 --- a/src/drivers/ao_mpu9250.h +++ b/src/drivers/ao_mpu9250.h @@ -102,21 +102,67 @@ # define MPU9250_ACCEL_CONFIG_AFS_SEL_16G 3 # define MPU9250_ACCEL_CONFIG_AFS_SEL_MASK 3 +#define MPU9250_MST_CTRL 0x24 +#define MPU9250_MST_CTRL_MULT_MST_EN 7 +#define MPU9250_MST_CTRL_WAIT_FOR_ES 6 +#define MPU9250_MST_CTRL_SLV_3_FIFO_EN 5 +#define MPU9250_MST_CTRL_I2C_MST_P_NSR 4 +#define MPU9250_MST_CTRL_I2C_MST_CLK 0 +#define MPU9250_MST_CTRL_I2C_MST_CLK_348 0 +#define MPU9250_MST_CTRL_I2C_MST_CLK_333 1 +#define MPU9250_MST_CTRL_I2C_MST_CLK_320 2 +#define MPU9250_MST_CTRL_I2C_MST_CLK_308 3 +#define MPU9250_MST_CTRL_I2C_MST_CLK_296 4 +#define MPU9250_MST_CTRL_I2C_MST_CLK_286 5 +#define MPU9250_MST_CTRL_I2C_MST_CLK_276 6 +#define MPU9250_MST_CTRL_I2C_MST_CLK_267 7 +#define MPU9250_MST_CTRL_I2C_MST_CLK_258 8 +#define MPU9250_MST_CTRL_I2C_MST_CLK_500 9 +#define MPU9250_MST_CTRL_I2C_MST_CLK_471 10 +#define MPU9250_MST_CTRL_I2C_MST_CLK_444 11 +#define MPU9250_MST_CTRL_I2C_MST_CLK_421 12 +#define MPU9250_MST_CTRL_I2C_MST_CLK_400 13 +#define MPU9250_MST_CTRL_I2C_MST_CLK_381 14 +#define MPU9250_MST_CTRL_I2C_MST_CLK_364 15 +#define MPU9250_MST_CTRL_I2C_MST_CLK_MASK 15 + +#define MPU9250_I2C_SLV0_ADDR 0x25 +#define MPU9250_I2C_SLV0_REG 0x26 +#define MPU9250_I2C_SLV0_CTRL 0x27 + +#define MPU9250_I2C_SLV1_ADDR 0x28 +#define MPU9250_I2C_SLV1_REG 0x29 +#define MPU9250_I2C_SLV1_CTRL 0x2a + +#define MPU9250_I2C_SLV2_ADDR 0x2b +#define MPU9250_I2C_SLV2_REG 0x2c +#define MPU9250_I2C_SLV2_CTRL 0x2d + +#define MPU9250_I2C_SLV3_ADDR 0x2e +#define MPU9250_I2C_SLV3_REG 0x2f +#define MPU9250_I2C_SLV3_CTRL 0x30 + +#define MPU9250_I2C_SLV4_ADDR 0x31 +#define MPU9250_I2C_SLV4_REG 0x32 +#define MPU9250_I2C_SLV4_DO 0x33 +#define MPU9250_I2C_SLV4_CTRL 0x34 +#define MPU9250_I2C_SLV4_DI 0x35 + +#define MPU9250_I2C_MST_STATUS 0x36 + +#define MPU9250_INT_PIN_CFG 0x37 + #define MPU9250_INT_ENABLE 0x38 -#define MPU9250_INT_ENABLE_FF_EN 7 -#define MPU9250_INT_ENABLE_MOT_EN 6 -#define MPU9250_INT_ENABLE_ZMOT_EN 5 +#define MPU9250_INT_ENABLE_WOM_EN 6 #define MPU9250_INT_ENABLE_FIFO_OFLOW_EN 4 -#define MPU9250_INT_ENABLE_I2C_MST_INT_EN 3 -#define MPU9250_INT_ENABLE_DATA_RDY_EN 0 +#define MPU9250_INT_ENABLE_FSYNC_INT_EN 3 +#define MPU9250_INT_ENABLE_RAW_RDY_EN 0 #define MPU9250_INT_STATUS 0x3a -#define MPU9250_INT_STATUS_FF_EN 7 -#define MPU9250_INT_STATUS_MOT_EN 6 -#define MPU9250_INT_STATUS_ZMOT_EN 5 -#define MPU9250_INT_STATUS_FIFO_OFLOW_EN 4 -#define MPU9250_INT_STATUS_I2C_MST_INT_EN 3 -#define MPU9250_INT_STATUS_DATA_RDY_EN 0 +#define MPU9250_INT_STATUS_WOM_INT 6 +#define MPU9250_INT_STATUS_FIFO_OFLOW_INT 4 +#define MPU9250_INT_STATUS_FSYNC_INT 3 +#define MPU9250_INT_STATUS_RAW_RDY_INT 0 #define MPU9250_ACCEL_XOUT_H 0x3b #define MPU9250_ACCEL_XOUT_L 0x3c @@ -194,6 +240,9 @@ struct ao_mpu9250_sample { int16_t gyro_x; int16_t gyro_y; int16_t gyro_z; + int16_t mag_x; + int16_t mag_y; + int16_t mag_z; }; extern struct ao_mpu9250_sample ao_mpu9250_current; |