diff options
| author | Keith Packard <keithp@keithp.com> | 2013-05-19 20:19:15 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2013-05-19 20:39:19 -0700 |
| commit | 07d261c08214837b5d5cac4d2be43e51a0c47868 (patch) | |
| tree | 144e86a0af4ea8008f2527a150394ac65a972ed9 | |
| parent | 3fe11b277dd7268eb445d120c8f9537f95148891 (diff) | |
altos/lpc: Fix beeper driver
Set prescale limit, not current prescale value (pr instead of pc).
Flip output 1 on PWM match (set emc toggle for channel 1).
Don't hold counter in reset (turn off CRST bit).
Signed-off-by: Keith Packard <keithp@keithp.com>
| -rw-r--r-- | src/lpc/ao_beep_lpc.c | 10 | ||||
| -rw-r--r-- | src/lpc/lpc.h | 10 |
2 files changed, 17 insertions, 3 deletions
diff --git a/src/lpc/ao_beep_lpc.c b/src/lpc/ao_beep_lpc.c index 281f981f..eb9132b8 100644 --- a/src/lpc/ao_beep_lpc.c +++ b/src/lpc/ao_beep_lpc.c @@ -29,16 +29,19 @@ ao_beep(uint8_t beep) /* Set prescaler to match cc1111 clocks */ - lpc_ct32b1.pc = AO_LPC_CLKOUT / 750000 - 1; + lpc_ct32b1.pr = AO_LPC_SYSCLK / 750000 - 1; /* Write the desired data in the match registers */ /* Reset after two time units */ lpc_ct32b1.mr[0] = beep << 1; - /* Flip output after one time unit */ + /* PWM width is half of that */ lpc_ct32b1.mr[1] = beep; + /* Flip output 1 on PWM match */ + lpc_ct32b1.emr = (LPC_CT32B_EMR_EMC_TOGGLE << LPC_CT32B_EMR_EMC1); + /* Reset on match 0 */ lpc_ct32b1.mcr = (1 << LPC_CT32B_MCR_MR0R); @@ -50,7 +53,7 @@ ao_beep(uint8_t beep) /* And turn the timer on */ lpc_ct32b1.tcr = ((1 << LPC_CT32B_TCR_CEN) | - (1 << LPC_CT32B_TCR_CRST)); + (0 << LPC_CT32B_TCR_CRST)); } } @@ -73,6 +76,7 @@ ao_beep_init(void) (LPC_IOCONF_MODE_INACTIVE << LPC_IOCONF_MODE) | (0 << LPC_IOCONF_HYS) | (0 << LPC_IOCONF_INV) | + (1 << LPC_IOCONF_ADMODE) | (0 << LPC_IOCONF_OD)); lpc_scb.sysahbclkctrl |= (1 << LPC_SCB_SYSAHBCLKCTRL_CT32B1); diff --git a/src/lpc/lpc.h b/src/lpc/lpc.h index 2493a1ff..1b48fcc9 100644 --- a/src/lpc/lpc.h +++ b/src/lpc/lpc.h @@ -1212,4 +1212,14 @@ extern struct lpc_ct32b lpc_ct32b0, lpc_ct32b1; #define LPC_CT32B_PWMC_PWMEN2 2 #define LPC_CT32B_PWMC_PWMEN3 3 +#define LPC_CT32B_EMR_EMC0 4 +#define LPC_CT32B_EMR_EMC1 6 +#define LPC_CT32B_EMR_EMC2 8 +#define LPC_CT32B_EMR_EMC3 10 + +#define LPC_CT32B_EMR_EMC_NOTHING 0 +#define LPC_CT32B_EMR_EMC_CLEAR 1 +#define LPC_CT32B_EMR_EMC_SET 2 +#define LPC_CT32B_EMR_EMC_TOGGLE 3 + #endif /* _LPC_H_ */ |