blob: eef14345dda7d5bf96a09881c61c6b27915c4975 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
|
/*
* Copyright © 2009 Keith Packard <keithp@keithp.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
*/
#include "ao.h"
static volatile __data uint16_t ao_tick_count;
uint16_t ao_time(void)
{
uint16_t v;
ao_arch_critical(
v = ao_tick_count;
);
return v;
}
static __xdata uint8_t ao_forever;
void
ao_delay(uint16_t ticks)
{
ao_alarm(ticks);
ao_sleep(&ao_forever);
}
#define T1_CLOCK_DIVISOR 8 /* 24e6/8 = 3e6 */
#define T1_SAMPLE_TIME 30000 /* 3e6/30000 = 100 */
#if HAS_ADC
volatile __data uint8_t ao_adc_interval = 1;
volatile __data uint8_t ao_adc_count;
#endif
void
ao_debug_out(char c);
ISR(TIMER1_COMPA_vect)
{
++ao_tick_count;
#if HAS_ADC
if (++ao_adc_count == ao_adc_interval) {
ao_adc_count = 0;
ao_adc_poll();
}
#endif
}
#if HAS_ADC
void
ao_timer_set_adc_interval(uint8_t interval) __critical
{
ao_adc_interval = interval;
ao_adc_count = 0;
}
#endif
void
ao_timer_init(void)
{
TCCR1A = ((0 << WGM11) | /* CTC mode, OCR1A */
(0 << WGM10)); /* CTC mode, OCR1A */
TCCR1B = ((0 << ICNC1) | /* no input capture noise canceler */
(0 << ICES1) | /* input capture on falling edge (don't care) */
(0 << WGM13) | /* CTC mode, OCR1A */
(1 << WGM12) | /* CTC mode, OCR1A */
(3 << CS10)); /* clk/64 from prescaler */
#if TEENSY
OCR1A = 2500; /* 16MHz clock */
#else
OCR1A = 1250; /* 8MHz clock */
#endif
TIMSK1 = (1 << OCIE1A); /* Interrupt on compare match */
}
|
