blob: 0d42b6d5cee511baf2160e18085815b9a37bb2c9 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
|
/*
* Copyright © 2011 Keith Packard <keithp@keithp.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
*/
#include "ao.h"
/*
* AltOS always cranks the clock to the max frequency
*/
void
ao_clock_init(void)
{
/* disable RC clock */
CLKSEL0 &= ~(1 << RCE);
/* Disable PLL */
PLLCSR &= ~(1 << PLLE);
/* Enable external clock */
CLKSEL0 |= (1 << EXTE);
/* wait for external clock to be ready */
while ((CLKSTA & (1 << EXTON)) == 0)
;
/* select external clock */
CLKSEL0 |= (1 << CLKS);
/* Disable the clock prescaler */
cli();
CLKPR = (1 << CLKPCE);
/* Always run the system clock at 8MHz */
#if AVR_CLOCK > 12000000UL
CLKPR = 1;
#else
CLKPR = 0;
#endif
sei();
/* Set up the PLL to use the crystal */
/* Use primary system clock as PLL source */
PLLFRQ = ((0 << PINMUX) | /* Use primary clock */
(0 << PLLUSB) | /* No divide by 2 for USB */
(0 << PLLTM0) | /* Disable high speed timer */
(0x4 << PDIV0)); /* 48MHz PLL clock */
/* Set the frequency of the crystal */
#if AVR_CLOCK > 12000000UL
PLLCSR |= (1 << PINDIV); /* For 16MHz crystal on Teensy board */
#else
PLLCSR &= ~(1 << PINDIV); /* For 8MHz crystal on TeleScience board */
#endif
/* Enable the PLL */
PLLCSR |= (1 << PLLE);
while (!(PLLCSR & (1 << PLOCK)))
;
set_sleep_mode(SLEEP_MODE_IDLE);
sleep_enable();
}
|
