/* * Copyright © 2012 Keith Packard * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. */ #ifndef _STM32L_H_ #define _STM32L_H_ #include typedef volatile uint32_t vuint32_t; struct stm_gpio { vuint32_t moder; vuint32_t otyper; vuint32_t ospeedr; vuint32_t pupdr; vuint32_t idr; vuint32_t odr; vuint32_t bsrr; vuint32_t lckr; vuint32_t afrl; vuint32_t afrh; }; #define STM_MODER_SHIFT(pin) ((pin) << 1) #define STM_MODER_MASK 3 #define STM_MODER_INPUT 0 #define STM_MODER_OUTPUT 1 #define STM_MODER_ALTERNATE 2 #define STM_MODER_ANALOG 3 static inline void stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) { gpio->moder = ((gpio->moder & ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) | value << STM_MODER_SHIFT(pin)); } static inline vuint32_t stm_moder_get(struct stm_gpio *gpio, int pin) { return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK; } #define STM_OTYPER_SHIFT(pin) (pin) #define STM_OTYPER_MASK 1 #define STM_OTYPER_PUSH_PULL 0 #define STM_OTYPER_OPEN_DRAIN 1 static inline void stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) { gpio->otyper = ((gpio->otyper & ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) | value << STM_OTYPER_SHIFT(pin)); } static inline vuint32_t stm_otyper_get(struct stm_gpio *gpio, int pin) { return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK; } #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1) #define STM_OSPEEDR_MASK 3 #define STM_OSPEEDR_400kHz 0 #define STM_OSPEEDR_2MHz 1 #define STM_OSPEEDR_10MHz 2 #define STM_OSPEEDR_40MHz 3 static inline void stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) { gpio->ospeedr = ((gpio->ospeedr & ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) | value << STM_OSPEEDR_SHIFT(pin)); } static inline vuint32_t stm_ospeedr_get(struct stm_gpio *gpio, int pin) { return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK; } #define STM_PUPDR_SHIFT(pin) ((pin) << 1) #define STM_PUPDR_MASK 3 #define STM_PUPDR_NONE 0 #define STM_PUPDR_PULL_UP 1 #define STM_PUPDR_PULL_DOWN 2 #define STM_PUPDR_RESERVED 3 static inline void stm_pupdr_set(struct stm_gpio *gpio, int pin, vuint32_t value) { gpio->pupdr = ((gpio->pupdr & ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) | value << STM_PUPDR_SHIFT(pin)); } static inline vuint32_t stm_pupdr_get(struct stm_gpio *gpio, int pin) { return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK; } #define STM_AFR_SHIFT(pin) ((pin) << 2) #define STM_AFR_MASK 0xf #define STM_AFR_NONE 0 #define STM_AFR_AF0 0x0 #define STM_AFR_AF1 0x1 #define STM_AFR_AF2 0x2 #define STM_AFR_AF3 0x3 #define STM_AFR_AF4 0x4 #define STM_AFR_AF5 0x5 #define STM_AFR_AF6 0x6 #define STM_AFR_AF7 0x7 #define STM_AFR_AF8 0x8 #define STM_AFR_AF9 0x9 #define STM_AFR_AF10 0xa #define STM_AFR_AF11 0xb #define STM_AFR_AF12 0xc #define STM_AFR_AF13 0xd #define STM_AFR_AF14 0xe #define STM_AFR_AF15 0xf static inline void stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) { if (pin < 8) gpio->afrl = ((gpio->afrl & ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) | value << STM_AFR_SHIFT(pin)); else { pin -= 8; gpio->afrh = ((gpio->afrh & ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) | value << STM_AFR_SHIFT(pin)); } } static inline uint32_t stm_afr_get(struct stm_gpio *gpio, int pin) { if (pin < 8) return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK; else { pin -= 8; return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK; } } extern struct stm_gpio stm_gpioa; extern struct stm_gpio stm_gpiob; extern struct stm_gpio stm_gpioc; extern struct stm_gpio stm_gpiod; extern struct stm_gpio stm_gpioe; extern struct stm_gpio stm_gpioh; struct stm_usart { vuint32_t sr; /* status register */ vuint32_t dr; /* data register */ vuint32_t brr; /* baud rate register */ vuint32_t cr1; /* control register 1 */ vuint32_t cr2; /* control register 2 */ vuint32_t cr3; /* control register 3 */ vuint32_t gtpr; /* guard time and prescaler */ }; extern struct stm_usart stm_usart1; #define STM_USART_SR_CTS (9) /* CTS flag */ #define STM_USART_SR_LBD (8) /* LIN break detection flag */ #define STM_USART_SR_TXE (7) /* Transmit data register empty */ #define STM_USART_SR_TC (6) /* Transmission complete */ #define STM_USART_SR_RXNE (5) /* Read data register not empty */ #define STM_USART_SR_IDLE (4) /* IDLE line detected */ #define STM_USART_SR_ORE (3) /* Overrun error */ #define STM_USART_SR_NF (2) /* Noise detected flag */ #define STM_USART_SR_FE (1) /* Framing error */ #define STM_USART_SR_PE (0) /* Parity error */ #define STM_USART_CR1_OVER8 (15) /* Oversampling mode */ #define STM_USART_CR1_UE (13) /* USART enable */ #define STM_USART_CR1_M (12) /* Word length */ #define STM_USART_CR1_WAKE (11) /* Wakeup method */ #define STM_USART_CR1_PCE (10) /* Parity control enable */ #define STM_USART_CR1_PS (9) /* Parity selection */ #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */ #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */ #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */ #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */ #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */ #define STM_USART_CR1_TE (3) /* Transmitter enable */ #define STM_USART_CR1_RE (2) /* Receiver enable */ #define STM_USART_CR1_RWU (1) /* Receiver wakeup */ #define STM_USART_CR1_SBK (0) /* Send break */ #define STM_USART_CR2_LINEN (14) /* LIN mode enable */ #define STM_USART_CR2_STOP (12) /* STOP bits */ #define STM_USART_CR2_STOP_MASK 3 #define STM_USART_CR2_STOP_1 0 #define STM_USART_CR2_STOP_0_5 1 #define STM_USART_CR2_STOP_2 2 #define STM_USART_CR2_STOP_1_5 3 #define STM_USART_CR2_CLKEN (11) /* Clock enable */ #define STM_USART_CR2_CPOL (10) /* Clock polarity */ #define STM_USART_CR2_CPHA (9) /* Clock phase */ #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */ #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */ #define STM_USART_CR2_LBDL (5) /* lin break detection length */ #define STM_USART_CR2_ADD (0) #define STM_USART_CR2_ADD_MASK 0xf #define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */ #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */ #define STM_USART_CR3_CTSE (9) /* CTS enable */ #define STM_USART_CR3_RTSE (8) /* RTS enable */ #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */ #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */ #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */ #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */ #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */ #define STM_USART_CR3_IRLP (2) /* IrDA low-power */ #define STM_USART_CR3_IREN (1) /* IrDA mode enable */ #define STM_USART_CR3_EIE (0) /* Error interrupt enable */ struct stm_spi { }; extern struct stm_spi stm_spi1; struct stm_tim { }; extern struct stm_tim stm_tim9; extern struct stm_tim stm_tim10; extern struct stm_tim stm_tim11; /* Flash interface */ struct stm_flash { vuint32_t acr; vuint32_t pecr; vuint32_t pdkeyr; vuint32_t pekeyr; vuint32_t prgkeyr; vuint32_t optkeyr; vuint32_t sr; vuint32_t obr; vuint32_t wrpr; }; extern struct stm_flash stm_flash; #define STM_FLASH_ACR_RUN_PD (4) #define STM_FLASH_ACR_SLEEP_PD (3) #define STM_FLASH_ACR_ACC64 (2) #define STM_FLASH_ACR_PRFEN (1) #define STM_FLASH_ACR_LATENCY (0) struct stm_rcc { vuint32_t cr; vuint32_t icscr; vuint32_t cfgr; vuint32_t cir; vuint32_t ahbrstr; vuint32_t apb2rstr; vuint32_t abp1rstr; vuint32_t ahbenr; vuint32_t apb2enr; vuint32_t apb1enr; vuint32_t ahblenr; vuint32_t apb2lpenr; vuint32_t apb1lpenr; vuint32_t csr; }; extern struct stm_rcc stm_rcc; #define STM_RCC_CR_RTCPRE (29) #define STM_RCC_CR_RTCPRE_HSE_DIV_2 0 #define STM_RCC_CR_RTCPRE_HSE_DIV_4 1 #define STM_RCC_CR_RTCPRE_HSE_DIV_8 2 #define STM_RCC_CR_RTCPRE_HSE_DIV_16 3 #define STM_RCC_CR_RTCPRE_HSE_MASK 3 #define STM_RCC_CR_CSSON (28) #define STM_RCC_CR_PLLRDY (25) #define STM_RCC_CR_PLLON (24) #define STM_RCC_CR_HSEBYP (18) #define STM_RCC_CR_HSERDY (17) #define STM_RCC_CR_HSEON (16) #define STM_RCC_CR_MSIRDY (9) #define STM_RCC_CR_MSION (8) #define STM_RCC_CR_HSIRDY (1) #define STM_RCC_CR_HSION (0) #define STM_RCC_CFGR_MCOPRE (28) #define STM_RCC_CFGR_MCOPRE_DIV_1 0 #define STM_RCC_CFGR_MCOPRE_DIV_2 1 #define STM_RCC_CFGR_MCOPRE_DIV_4 2 #define STM_RCC_CFGR_MCOPRE_DIV_8 3 #define STM_RCC_CFGR_MCOPRE_DIV_16 4 #define STM_RCC_CFGR_MCOPRE_DIV_MASK 7 #define STM_RCC_CFGR_MCOSEL (24) #define STM_RCC_CFGR_MCOSEL_DISABLE 0 #define STM_RCC_CFGR_MCOSEL_SYSCLK 1 #define STM_RCC_CFGR_MCOSEL_HSI 2 #define STM_RCC_CFGR_MCOSEL_MSI 3 #define STM_RCC_CFGR_MCOSEL_HSE 4 #define STM_RCC_CFGR_MCOSEL_PLL 5 #define STM_RCC_CFGR_MCOSEL_LSI 6 #define STM_RCC_CFGR_MCOSEL_LSE 7 #define STM_RCC_CFGR_MCOSEL_MASK 7 #define STM_RCC_CFGR_PLLDIV (22) #define STM_RCC_CFGR_PLLDIV_2 1 #define STM_RCC_CFGR_PLLDIV_3 2 #define STM_RCC_CFGR_PLLDIV_4 3 #define STM_RCC_CFGR_PLLDIV_MASK 3 #define STM_RCC_CFGR_PLLMUL (18) #define STM_RCC_CFGR_PLLMUL_3 0 #define STM_RCC_CFGR_PLLMUL_4 1 #define STM_RCC_CFGR_PLLMUL_6 2 #define STM_RCC_CFGR_PLLMUL_8 3 #define STM_RCC_CFGR_PLLMUL_12 4 #define STM_RCC_CFGR_PLLMUL_16 5 #define STM_RCC_CFGR_PLLMUL_24 6 #define STM_RCC_CFGR_PLLMUL_32 7 #define STM_RCC_CFGR_PLLMUL_48 8 #define STM_RCC_CFGR_PLLMUL_MASK 0xf #define STM_RCC_CFGR_PLLSRC (16) #define STM_RCC_CFGR_PPRE2 (11) #define STM_RCC_CFGR_PPRE2_DIV_1 0 #define STM_RCC_CFGR_PPRE2_DIV_2 4 #define STM_RCC_CFGR_PPRE2_DIV_4 5 #define STM_RCC_CFGR_PPRE2_DIV_8 6 #define STM_RCC_CFGR_PPRE2_DIV_16 7 #define STM_RCC_CFGR_PPRE2_MASK 7 #define STM_RCC_CFGR_PPRE1 (8) #define STM_RCC_CFGR_PPRE1_DIV_1 0 #define STM_RCC_CFGR_PPRE1_DIV_2 4 #define STM_RCC_CFGR_PPRE1_DIV_4 5 #define STM_RCC_CFGR_PPRE1_DIV_8 6 #define STM_RCC_CFGR_PPRE1_DIV_16 7 #define STM_RCC_CFGR_PPRE1_MASK 7 #define STM_RCC_CFGR_HPRE (4) #define STM_RCC_CFGR_HPRE_DIV_1 0 #define STM_RCC_CFGR_HPRE_DIV_2 8 #define STM_RCC_CFGR_HPRE_DIV_4 9 #define STM_RCC_CFGR_HPRE_DIV_8 0xa #define STM_RCC_CFGR_HPRE_DIV_16 0xb #define STM_RCC_CFGR_HPRE_DIV_64 0xc #define STM_RCC_CFGR_HPRE_DIV_128 0xd #define STM_RCC_CFGR_HPRE_DIV_256 0xe #define STM_RCC_CFGR_HPRE_DIV_512 0xf #define STM_RCC_CFGR_HPRE_MASK 0xf #define STM_RCC_CFGR_SWS (2) #define STM_RCC_CFGR_SWS_MSI 0 #define STM_RCC_CFGR_SWS_HSI 1 #define STM_RCC_CFGR_SWS_HSE 2 #define STM_RCC_CFGR_SWS_PLL 3 #define STM_RCC_CFGR_SWS_MASK 3 #define STM_RCC_CFGR_SW (0) #define STM_RCC_CFGR_SW_MSI 0 #define STM_RCC_CFGR_SW_HSI 1 #define STM_RCC_CFGR_SW_HSE 2 #define STM_RCC_CFGR_SW_PLL 3 #define STM_RCC_CFGR_SW_MASK 3 #define STM_RCC_AHBENR_DMA1EN (24) #define STM_RCC_AHBENR_FLITFEN (15) #define STM_RCC_AHBENR_CRCEN (12) #define STM_RCC_AHBENR_GPIOHEN (5) #define STM_RCC_AHBENR_GPIOEEN (4) #define STM_RCC_AHBENR_GPIODEN (3) #define STM_RCC_AHBENR_GPIOCEN (2) #define STM_RCC_AHBENR_GPIOBEN (1) #define STM_RCC_AHBENR_GPIOAEN (0) #define STM_RCC_APB2ENR_USART1EN (14) #define STM_RCC_APB2ENR_SPI1EN (12) #define STM_RCC_APB2ENR_ADC1EN (9) #define STM_RCC_APB2ENR_TIM11EN (4) #define STM_RCC_APB2ENR_TIM10EN (3) #define STM_RCC_APB2ENR_TIM9EN (2) #define STM_RCC_APB2ENR_SYSCFGEN (0) #define STM_RCC_APB1ENR_COMPEN (31) #define STM_RCC_APB1ENR_DACEN (29) #define STM_RCC_APB1ENR_PWREN (28) #define STM_RCC_APB1ENR_USBEN (23) #define STM_RCC_APB1ENR_I2C2EN (22) #define STM_RCC_APB1ENR_I2C1EN (21) #define STM_RCC_APB1ENR_USART3EN (18) #define STM_RCC_APB1ENR_USART2EN (17) #define STM_RCC_APB1ENR_SPI2EN (14) #define STM_RCC_APB1ENR_WWDGEN (11) #define STM_RCC_APB1ENR_LCDEN (9) #define STM_RCC_APB1ENR_TIM7EN (5) #define STM_RCC_APB1ENR_TIM6EN (4) #define STM_RCC_APB1ENR_TIM4EN (2) #define STM_RCC_APB1ENR_TIM3EN (1) #define STM_RCC_APB1ENR_TIM2EN (0) struct stm_pwr { vuint32_t cr; vuint32_t csr; }; extern struct stm_pwr stm_pwr; #define STM_PWR_CR_LPRUN (14) #define STM_PWR_CR_VOS (11) #define STM_PWR_CR_VOS_1_8 1 #define STM_PWR_CR_VOS_1_5 2 #define STM_PWR_CR_VOS_1_2 3 #define STM_PWR_CR_VOS_MASK 3 #define STM_PWR_CR_FWU (10) #define STM_PWR_CR_ULP (9) #define STM_PWR_CR_DBP (8) #define STM_PWR_CR_PLS (5) #define STM_PWR_CR_PLS_1_9 0 #define STM_PWR_CR_PLS_2_1 1 #define STM_PWR_CR_PLS_2_3 2 #define STM_PWR_CR_PLS_2_5 3 #define STM_PWR_CR_PLS_2_7 4 #define STM_PWR_CR_PLS_2_9 5 #define STM_PWR_CR_PLS_3_1 6 #define STM_PWR_CR_PLS_EXT 7 #define STM_PWR_CR_PLS_MASK 7 #define STM_PWR_CR_PVDE (4) #define STM_PWR_CR_CSBF (3) #define STM_PWR_CR_CWUF (2) #define STM_PWR_CR_PDDS (1) #define STM_PWR_CR_LPSDSR (0) #define STM_PWR_CSR_EWUP3 (10) #define STM_PWR_CSR_EWUP2 (9) #define STM_PWR_CSR_EWUP1 (8) #define STM_PWR_CSR_REGLPF (5) #define STM_PWR_CSR_VOSF (4) #define STM_PWR_CSR_VREFINTRDYF (3) #define STM_PWR_CSR_PVDO (2) #define STM_PWR_CSR_SBF (1) #define STM_PWR_CSR_WUF (0) struct stm_tim67 { vuint32_t cr1; vuint32_t cr2; uint32_t _unused_08; vuint32_t dier; vuint32_t sr; vuint32_t egr; uint32_t _unused_18; uint32_t _unused_1c; uint32_t _unused_20; vuint32_t cnt; vuint32_t psc; vuint32_t arr; }; extern struct stm_tim67 stm_tim6; #define STM_TIM67_CR1_ARPE (7) #define STM_TIM67_CR1_OPM (3) #define STM_TIM67_CR1_URS (2) #define STM_TIM67_CR1_UDIS (1) #define STM_TIM67_CR1_CEN (0) #define STM_TIM67_CR2_MMS (4) #define STM_TIM67_CR2_MMS_RESET 0 #define STM_TIM67_CR2_MMS_ENABLE 1 #define STM_TIM67_CR2_MMS_UPDATE 2 #define STM_TIM67_CR2_MMS_MASK 7 #define STM_TIM67_DIER_UDE (8) #define STM_TIM67_DIER_UIE (0) #define STM_TIM67_SR_UIF (0) #define STM_TIM67_EGR_UG (0) struct stm_nvic { vuint32_t iser[3]; /* 0x000 */ uint8_t _unused00c[0x080 - 0x00c]; vuint32_t icer[3]; /* 0x080 */ uint8_t _unused08c[0x100 - 0x08c]; vuint32_t ispr[3]; /* 0x100 */ uint8_t _unused10c[0x180 - 0x10c]; vuint32_t icpr[3]; /* 0x180 */ uint8_t _unused18c[0x200 - 0x18c]; vuint32_t iabr[3]; /* 0x200 */ uint8_t _unused20c[0x300 - 0x20c]; vuint32_t ipr[21]; /* 0x300 */ uint8_t _unused324[0xe00 - 0x324]; vuint32_t stir; /* 0xe00 */ }; extern struct stm_nvic stm_nvic; #define IRQ_REG(irq) ((irq) >> 5) #define IRQ_BIT(irq) ((irq) & 0x1f) #define IRQ_MASK(irq) (1 << IRQ_BIT(irq)) #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1) static inline void stm_nvic_set_enable(int irq) { stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq); } static inline void stm_nvic_clear_enable(int irq) { stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq); } static inline int stm_nvic_enabled(int irq) { return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq); } static inline void stm_nvic_set_pending(int irq) { stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq); } static inline void stm_nvic_clear_pending(int irq) { stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq); } static inline int stm_nvic_pending(int irq) { return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq); } static inline int stm_nvic_active(int irq) { return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq); } #define IRQ_PRIO_REG(irq) ((irq) >> 2) #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3) #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq)) static inline void stm_nvic_set_priority(int irq, uint8_t prio) { int n = IRQ_PRIO_REG(irq); uint32_t v; v = stm_nvic.ipr[n]; v &= ~IRQ_PRIO_MASK(irq); v |= (prio) << IRQ_PRIO_BIT(irq); stm_nvic.ipr[n] = v; } static inline uint8_t stm_nvic_get_priority(int irq) { return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0); } #define isr(name) void stm_ ## name ## _isr(void); isr(nmi) isr(hardfault) isr(memmanage) isr(busfault) isr(usagefault) isr(svc) isr(debugmon) isr(pendsv) isr(systick) isr(wwdg) isr(pvd) isr(tamper_stamp) isr(rtc_wkup) isr(flash) isr(rcc) isr(exti0) isr(exti1) isr(exti2) isr(exti3) isr(exti4) isr(dma1_channel1) isr(dma1_channel2) isr(dma1_channel3) isr(dma1_channel4) isr(dma1_channel5) isr(dma1_channel6) isr(dma1_channel7) isr(adc1) isr(usb_hp) isr(usb_lp) isr(dac) isr(comp) isr(exti9_5) isr(lcd) isr(tim9) isr(tim10) isr(tim11) isr(tim2) isr(tim3) isr(tim4) isr(i2c1_ev) isr(i2c1_er) isr(i2c2_ev) isr(i2c2_er) isr(spi1) isr(spi2) isr(usart1) isr(usart2) isr(usart3) isr(exti15_10) isr(rtc_alarm) isr(usb_fs_wkup) isr(tim6) isr(tim7) #define STM_ISR_TIM6_POS 43 #undef isr #endif /* _STM32L_H_ */