From 9025eb792861930e6af918d2727c4f5d97a69936 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 19 Dec 2008 21:11:45 -0800 Subject: Autotools. Signed-off-by: Keith Packard --- target/blink/Makefile | 44 ++++++++++++++++++++++ target/blink/blink.c | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++ target/isr.c | 90 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 234 insertions(+) create mode 100644 target/blink/Makefile create mode 100644 target/blink/blink.c create mode 100644 target/isr.c (limited to 'target') diff --git a/target/blink/Makefile b/target/blink/Makefile new file mode 100644 index 00000000..1f18f529 --- /dev/null +++ b/target/blink/Makefile @@ -0,0 +1,44 @@ +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse \ + --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large $(DEBUG) --less-pedantic \ + --no-peep --int-long-reent --float-reent \ + --data-loc 0x30 + +LDFLAGS=-L/usr/share/sdcc/lib/large --out-fmt-ihx +LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf400 --xram-size 1024 + +LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 + +SRC=blink.c +ADB=$(SRC:.c=.adb) +ASM=$(SRC:.c=.asm) +LNK=$(SRC:.c=.lnk) +LST=$(SRC:.c=.lst) +REL=$(SRC:.c=.rel) +RST=$(SRC:.c=.rst) +SYM=$(SRC:.c=.sym) + +PROGS=blink-flash.ihx blink-ram.ihx +PCDB=$(PROGS:.ihx=.cdb) +PLNK=$(PROGS:.ihx=.lnk) +PMAP=$(PROGS:.ihx=.map) +PMEM=$(PROGS:.ihx=.mem) +PAOM=$(PROGS:.ihx=) + +%.rel : %.c + $(CC) -c $(CFLAGS) -o$*.rel $< + +all: $(PROGS) + +blink-ram.ihx: $(REL) Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o blink-ram.ihx $(REL) + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o blink-flash.ihx $(REL) + +blink-flash.ihx: blink-ram.ihx + +clean: + rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) + rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) diff --git a/target/blink/blink.c b/target/blink/blink.c new file mode 100644 index 00000000..907c82b8 --- /dev/null +++ b/target/blink/blink.c @@ -0,0 +1,100 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +sfr at 0x80 P0; +sfr at 0x90 P1; +sfr at 0xA0 P2; +sfr at 0xC6 CLKCON; + +sfr at 0xF1 PERCFG; +sfr at 0xF2 ADCCFG; +sfr at 0xF3 P0SEL; +sfr at 0xF4 P1SEL; +sfr at 0xF5 P2SEL; + +sfr at 0xFD P0DIR; +sfr at 0xFE P1DIR; +sfr at 0xFF P2DIR; +sfr at 0x8F P0INP; +sfr at 0xF6 P1INP; +sfr at 0xF7 P2INP; + +sfr at 0x89 P0IFG; +sfr at 0x8A P1IFG; +sfr at 0x8B P2IFG; + +#define nop() _asm nop _endasm; + +void +delay (unsigned char n) +{ + unsigned char i = 0, j = 0; + + n <<= 1; + while (--n != 0) + while (--j != 0) + while (--i != 0) + nop(); +} + +void +dit() { + P1 = 0xff; + delay(1); + P1 = 0xfd; + delay(1); +} + +void +dah () { + P1 = 0xff; + delay(3); + P1 = 0xfd; + delay(1); +} + +void +charspace () { + delay(2); +} + +void +wordspace () { + delay(8); +} + +#define _ dit(); +#define ___ dah(); +#define C charspace(); +#define W wordspace(); + +main () +{ + CLKCON = 0; + /* Set p1_1 to output */ + P1DIR = 0x02; + P1INP = 0x00; + P2INP = 0x00; + for (;;) { + ___ _ ___ _ C ___ ___ _ ___ W /* cq */ + ___ _ _ C _ W /* de */ + ___ _ ___ C ___ _ _ C /* kd */ + ___ ___ _ _ _ C _ _ _ C /* 7s */ + ___ ___ _ ___ C ___ ___ _ W /* qg */ + } +} diff --git a/target/isr.c b/target/isr.c new file mode 100644 index 00000000..43aedc29 --- /dev/null +++ b/target/isr.c @@ -0,0 +1,90 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +void rftxrx_isr (void) __interrupt(0) __using(1) +{ +} + +void adc_isr (void) __interrupt(1) __using(1) +{ +} + +void urx0_isr (void) __interrupt(2) __using(1) +{ +} + +void urx1_isr (void) __interrupt(3) __using(1) +{ +} + +void enc_isr (void) __interrupt(4) __using(1) +{ +} + +void st_isr (void) __interrupt(5) __using(1) +{ +} + +void usb_isr (void) __interrupt(6) __using(1) +{ +} + +void utx0_isr (void) __interrupt(7) __using(1) +{ +} + +void dma_isr (void) __interrupt(8) __using(1) +{ +} + +void t1_isr (void) __interrupt(9) __using(1) +{ +} + +void t2_isr (void) __interrupt(10) __using(1) +{ +} + +void t3_isr (void) __interrupt(11) __using(1) +{ +} + +void t4_isr (void) __interrupt(12) __using(1) +{ +} + +void p0int_isr (void) __interrupt(13) __using(1) +{ +} + +void utx1_isr (void) __interrupt(14) __using(1) +{ +} + +void p1int_isr (void) __interrupt(15) __using(1) +{ +} + +void rf_isr (void) __interrupt(16) __using(1) +{ +} + +void wdt_isr (void) __interrupt(17) __using(1) +{ +} + -- cgit v1.2.3 From 30f23f23a6db3d12fdc9c088cf6ab47c5e5077fb Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 19 Dec 2008 21:13:04 -0800 Subject: Clean up autotools stuff. Signed-off-by: Keith Packard --- .gitignore | 32 +++++++++-------- ccload/.gitignore | 1 + configure.ac | 95 +++++++++++++++++++++++++++++++++++++++++++++++++ target/blink/.gitignore | 13 +++++++ 4 files changed, 127 insertions(+), 14 deletions(-) create mode 100644 ccload/.gitignore create mode 100644 configure.ac create mode 100644 target/blink/.gitignore (limited to 'target') diff --git a/.gitignore b/.gitignore index 4db91cd2..93d05b7f 100644 --- a/.gitignore +++ b/.gitignore @@ -1,16 +1,20 @@ -ccdbg -*.ihx -blink-flash -blink-ram *.o +*.a +.deps tags -*.adb -*.asm -*.cdb -*.lnk -*.lst -*.map -*.mem -*.rel -*.rst -*.sym +Makefile +Makefile.in +aclocal.m4 +autom4te.cache +config.h +config.h.in +config.h.in~ +config.log +config.status +configure +depcomp +install-sh +Makefile.in +missing +stamp-h1 + diff --git a/ccload/.gitignore b/ccload/.gitignore new file mode 100644 index 00000000..3899747a --- /dev/null +++ b/ccload/.gitignore @@ -0,0 +1 @@ +ccload diff --git a/configure.ac b/configure.ac new file mode 100644 index 00000000..6182d71c --- /dev/null +++ b/configure.ac @@ -0,0 +1,95 @@ +dnl +dnl Copyright © 2008 Keith Packard +dnl +dnl This program is free software; you can redistribute it and/or modify +dnl it under the terms of the GNU General Public License as published by +dnl the Free Software Foundation; either version 2 of the License, or +dnl (at your option) any later version. +dnl +dnl This program is distributed in the hope that it will be useful, but +dnl WITHOUT ANY WARRANTY; without even the implied warranty of +dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +dnl General Public License for more details. +dnl +dnl You should have received a copy of the GNU General Public License along +dnl with this program; if not, write to the Free Software Foundation, Inc., +dnl 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +dnl +dnl Process this file with autoconf to create configure. + +AC_INIT(COPYING) + +AM_INIT_AUTOMAKE(cctools, 0.1) +AM_MAINTAINER_MODE + +dnl ========================================================================== + +AM_CONFIG_HEADER(config.h) + +AC_PROG_CC +AC_PROG_INSTALL +AC_PROG_LN_S +AC_PROG_RANLIB + +WARN_CFLAGS="" +if test "x$GCC" = "xyes"; then + WARN_CFLAGS="-Wall -Wpointer-arith -Wstrict-prototypes \ + -Wmissing-prototypes -Wmissing-declarations \ + -Wnested-externs -fno-strict-aliasing" + AC_DEFINE_UNQUOTED(HAVE_WARNING_CPP_DIRECTIVE,1, + [Can use #warning in C files]) +fi +AC_SUBST(WARN_CFLAGS) + +dnl ========================================================================== + +AM_CONDITIONAL(CROSS_COMPILING, test $cross_compiling = yes) + +dnl ========================================================================== + +# Setup for compiling build tools (fc-glyphname, etc) +AC_MSG_CHECKING([for a C compiler for build tools]) +if test $cross_compiling = yes; then + AC_CHECK_PROGS(CC_FOR_BUILD, gcc cc) +else + CC_FOR_BUILD=$CC +fi +AC_MSG_RESULT([$CC_FOR_BUILD]) +AC_SUBST(CC_FOR_BUILD) + +AC_MSG_CHECKING([for suffix of executable build tools]) +if test $cross_compiling = yes; then + cat >conftest.c <<\_______EOF +int +main () +{ + exit (0); +} +_______EOF + for i in .exe ""; do + compile="$CC_FOR_BUILD conftest.c -o conftest$i" + if AC_TRY_EVAL(compile); then + if (./conftest) 2>&AC_FD_CC; then + EXEEXT_FOR_BUILD=$i + break + fi + fi + done + rm -f conftest* + if test "${EXEEXT_FOR_BUILD+set}" != set; then + AC_MSG_ERROR([Cannot determine suffix of executable build tools]) + fi +else + EXEEXT_FOR_BUILD=$EXEEXT +fi +AC_MSG_RESULT([$EXEEXT_FOR_BUILD]) +AC_SUBST(EXEEXT_FOR_BUILD) + +USB_LIBS="-lusb" +AC_SUBST(USB_LIBS) + +AC_OUTPUT([ +Makefile +lib/Makefile +ccload/Makefile +]) diff --git a/target/blink/.gitignore b/target/blink/.gitignore new file mode 100644 index 00000000..40f72de9 --- /dev/null +++ b/target/blink/.gitignore @@ -0,0 +1,13 @@ +*.ihx +*.adb +*.asm +*.cdb +*.lnk +*.lst +*.map +*.mem +*.rel +*.rst +*.sym +blink-flash +blink-ram -- cgit v1.2.3 From ea366058aa467a8a7caf17e7014758f3741ea7f7 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Mon, 29 Dec 2008 12:35:11 -0800 Subject: Fix flashing less than a full page of data. Verify page at a time. The 8051 flashing code requires special help with counts with non-zero low byte. Also, instead of verifying the entire flash contents at the end, verify each page as it goes. Signed-off-by: Keith Packard --- ccload/ccload.c | 2 ++ lib/ccdbg-flash.c | 61 ++++++++++++++++++++++++++++++++------------------- target/blink/Makefile | 2 ++ 3 files changed, 42 insertions(+), 23 deletions(-) (limited to 'target') diff --git a/ccload/ccload.c b/ccload/ccload.c index b4bb1443..3e220914 100644 --- a/ccload/ccload.c +++ b/ccload/ccload.c @@ -54,6 +54,8 @@ main (int argc, char **argv) if (!dbg) exit (1); + ccdbg_add_debug(CC_DEBUG_FLASH); + ccdbg_debug_mode(dbg); ccdbg_halt(dbg); if (image->address == 0xf000) { diff --git a/lib/ccdbg-flash.c b/lib/ccdbg-flash.c index f950dd1b..8b3390c7 100644 --- a/lib/ccdbg-flash.c +++ b/lib/ccdbg-flash.c @@ -244,13 +244,16 @@ ccdbg_flash_hex_image(struct ccdbg *dbg, struct hex_image *image) uint16_t flash_prog; uint16_t flash_len; uint8_t fwt; + uint16_t flash_addr; uint16_t flash_word_addr; uint16_t flash_words; + uint8_t flash_words_high, flash_words_low; uint16_t ram_addr; uint16_t pc; uint8_t status; uint16_t remain, this_time, start; uint8_t verify[0x400]; + int times; ccdbg_clock_init(dbg); if (image->address + image->length > 0x8000) { @@ -286,52 +289,64 @@ ccdbg_flash_hex_image(struct ccdbg *dbg, struct hex_image *image) ccdbg_debug(CC_DEBUG_FLASH, "Upload %d bytes at 0x%04x\n", this_time, ram_addr); ccdbg_write_memory(dbg, ram_addr, image->data + start, this_time); - ccdbg_debug(CC_DEBUG_FLASH, "Verify %d bytes\n", image->length); + ccdbg_debug(CC_DEBUG_FLASH, "Verify %d bytes in ram\n", this_time); ccdbg_read_memory(dbg, ram_addr, verify, this_time); if (memcmp (image->data + start, verify, this_time) != 0) { - fprintf(stderr, "image verify failed\n"); + fprintf(stderr, "ram verify failed\n"); return 1; } - flash_word_addr = (image->address + start) >> 1; + flash_addr = image->address + start; + flash_word_addr = flash_addr >> 1; flash_len = this_time + (this_time & 1); flash_words = flash_len >> 1; + flash_words_low = flash_words & 0xff; + flash_words_high = flash_words >> 8; + + /* The flash code above is lame */ + if (flash_words_low) + flash_words_high++; + ccdbg_write_uint8(dbg, flash_prog + FLASH_ADDR_HIGH, flash_word_addr >> 8); ccdbg_write_uint8(dbg, flash_prog + FLASH_ADDR_LOW, flash_word_addr & 0xff); ccdbg_write_uint8(dbg, flash_prog + RAM_ADDR_HIGH, ram_addr >> 8); ccdbg_write_uint8(dbg, flash_prog + RAM_ADDR_LOW, ram_addr & 0xff); - ccdbg_write_uint8(dbg, flash_prog + FLASH_WORDS_HIGH, flash_words >> 8); - ccdbg_write_uint8(dbg, flash_prog + FLASH_WORDS_LOW, flash_words & 0xff); + ccdbg_write_uint8(dbg, flash_prog + FLASH_WORDS_HIGH, flash_words_high); + ccdbg_write_uint8(dbg, flash_prog + FLASH_WORDS_LOW, flash_words_low); ccdbg_set_pc(dbg, flash_prog); pc = ccdbg_get_pc(dbg); - ccdbg_debug(CC_DEBUG_FLASH, "Starting flash program at 0x%04x\n", pc); + ccdbg_debug(CC_DEBUG_FLASH, "Flashing %d bytes at 0x%04x\n", + this_time, flash_addr); status = ccdbg_resume(dbg); - ccdbg_debug(CC_DEBUG_FLASH, "resume status is 0x%02x\n", status); - do { + for (times = 0; times < 10; times++) { status = ccdbg_read_status(dbg); ccdbg_debug(CC_DEBUG_FLASH, "chip status is 0x%02x\n", status); - sleep(1); - } while ((status & CC_STATUS_CPU_HALTED) == 0); + if ((status & CC_STATUS_CPU_HALTED) != 0) + break; + } + if (times == 10) { + fprintf(stderr, "flash page timed out\n"); + return 1; + } + ccdbg_debug(CC_DEBUG_FLASH, "Verify %d bytes in flash\n", this_time); + ccdbg_read_memory(dbg, flash_addr, verify, this_time); + if (memcmp (image->data + start, verify, this_time) != 0) { + int i; + fprintf(stderr, "flash verify failed\n"); + for (i = 0; i < this_time; i++) { + if (image->data[start + i] != verify[i]) + fprintf(stderr, "0x%04x: 0x%02x != 0x%02x\n", + start + i, image->data[start+i], verify[i]); + } + return 1; + } remain -= this_time; start += this_time; } -#if 1 - ccdbg_debug(CC_DEBUG_FLASH, "Downloading flash to check\n"); - struct hex_image *test_image; - test_image = ccdbg_read_hex_image(dbg, image->address, image->length); - if (!ccdbg_hex_image_equal(image, test_image)) { - int i; - fprintf(stderr, "Image not loaded\n"); - for (i = 0;i < 0x10; i++) - ccdbg_debug(CC_DEBUG_FLASH, "0x%02x : 0x%02x\n", image->data[i], test_image->data[i]); - return 1; - } - return 0; -#endif return 0; } diff --git a/target/blink/Makefile b/target/blink/Makefile index 1f18f529..4c9b4102 100644 --- a/target/blink/Makefile +++ b/target/blink/Makefile @@ -42,3 +42,5 @@ blink-flash.ihx: blink-ram.ihx clean: rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) + +install: -- cgit v1.2.3 From 7c03937b36aac82b08f4ea0c6da33a994fe15ec7 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 30 Dec 2008 22:40:13 -0800 Subject: Add simple and timer sample programs Signed-off-by: Keith Packard --- target/simple/Makefile | 44 ++++++++ target/simple/simple.c | 42 +++++++ target/timer/Makefile | 44 ++++++++ target/timer/cc1111.h | 294 +++++++++++++++++++++++++++++++++++++++++++++++++ target/timer/timer.c | 55 +++++++++ 5 files changed, 479 insertions(+) create mode 100644 target/simple/Makefile create mode 100644 target/simple/simple.c create mode 100644 target/timer/Makefile create mode 100644 target/timer/cc1111.h create mode 100644 target/timer/timer.c (limited to 'target') diff --git a/target/simple/Makefile b/target/simple/Makefile new file mode 100644 index 00000000..c4432325 --- /dev/null +++ b/target/simple/Makefile @@ -0,0 +1,44 @@ +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse \ + --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large $(DEBUG) --less-pedantic \ + --no-peep --int-long-reent --float-reent \ + --data-loc 0x30 + +LDFLAGS=-L/usr/share/sdcc/lib/large --out-fmt-ihx +LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf400 --xram-size 1024 + +LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 + +SRC=simple.c +ADB=$(SRC:.c=.adb) +ASM=$(SRC:.c=.asm) +LNK=$(SRC:.c=.lnk) +LST=$(SRC:.c=.lst) +REL=$(SRC:.c=.rel) +RST=$(SRC:.c=.rst) +SYM=$(SRC:.c=.sym) + +PROGS=simple-flash.ihx simple-ram.ihx +PCDB=$(PROGS:.ihx=.cdb) +PLNK=$(PROGS:.ihx=.lnk) +PMAP=$(PROGS:.ihx=.map) +PMEM=$(PROGS:.ihx=.mem) +PAOM=$(PROGS:.ihx=) + +%.rel : %.c + $(CC) -c $(CFLAGS) -o$*.rel $< + +all: $(PROGS) + +simple-ram.ihx: $(REL) Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o simple-ram.ihx $(REL) + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o simple-flash.ihx $(REL) + +simple-flash.ihx: simple-ram.ihx + +clean: + rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) + rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) diff --git a/target/simple/simple.c b/target/simple/simple.c new file mode 100644 index 00000000..b7ea1019 --- /dev/null +++ b/target/simple/simple.c @@ -0,0 +1,42 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +sfr at 0x90 P1; +sfr at 0xC6 CLKCON; + +sfr at 0xFE P1DIR; +sfr at 0xF6 P1INP; + +void delay(int n) __reentrant +{ + while (n--) + _asm nop _endasm; +} +int +main (void) __reentrant +{ + long i; + CLKCON = 0; + /* Set p1_1 to output */ + P1DIR = 0x02; + for (;;) { + P1 ^= 0x2; + for (i = 0; i < 1000; i++) + delay(1000); + } +} diff --git a/target/timer/Makefile b/target/timer/Makefile new file mode 100644 index 00000000..99e06b8d --- /dev/null +++ b/target/timer/Makefile @@ -0,0 +1,44 @@ +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse \ + --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large $(DEBUG) --less-pedantic \ + --no-peep --int-long-reent --float-reent \ + --data-loc 0x30 + +LDFLAGS=-L/usr/share/sdcc/lib/large --out-fmt-ihx +LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf400 --xram-size 1024 + +LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 + +SRC=timer.c +ADB=$(SRC:.c=.adb) +ASM=$(SRC:.c=.asm) +LNK=$(SRC:.c=.lnk) +LST=$(SRC:.c=.lst) +REL=$(SRC:.c=.rel) +RST=$(SRC:.c=.rst) +SYM=$(SRC:.c=.sym) + +PROGS=timer-flash.ihx timer-ram.ihx +PCDB=$(PROGS:.ihx=.cdb) +PLNK=$(PROGS:.ihx=.lnk) +PMAP=$(PROGS:.ihx=.map) +PMEM=$(PROGS:.ihx=.mem) +PAOM=$(PROGS:.ihx=) + +%.rel : %.c + $(CC) -c $(CFLAGS) -o$*.rel $< + +all: $(PROGS) + +timer-ram.ihx: $(REL) Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o timer-ram.ihx $(REL) + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o timer-flash.ihx $(REL) + +timer-flash.ihx: timer-ram.ihx + +clean: + rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) + rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) diff --git a/target/timer/cc1111.h b/target/timer/cc1111.h new file mode 100644 index 00000000..7a531cc0 --- /dev/null +++ b/target/timer/cc1111.h @@ -0,0 +1,294 @@ +/*------------------------------------------------------------------------- + Register Declarations for the ChipCon CC1111 Processor Range + + Copyright © 2008 Keith Packard + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + Adapted from the Cygnal C8051F12x config file which is: + + Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef _CC1111_H_ +#define _CC1111_H_ + + +/* BYTE Registers */ + +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x84 DPL1 ; /* DATA POINTER 1 - LOW BYTE */ +sfr at 0x85 DPH1 ; /* DATA POINTER 1 - HIGH BYTE */ +sfr at 0x86 U0CSR ; /* USART 0 Control and status */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 P0IFG ; /* TIMER MODE */ +sfr at 0x8A P1IFG ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B P2IFG ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C PICTL ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D P1IEN ; /* TIMER 1 - HIGH BYTE */ + +sfr at 0x8F P0INP ; /* FLASH WRITE/ERASE CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0x91 RFIM ; /* UART 0 STATUS */ +sfr at 0x92 DPS ; /* */ +sfr at 0x93 MPAGE ; /* */ +sfr at 0x94 _SFR94_ ; /* */ +sfr at 0x95 ENDIAN ; /* */ +sfr at 0x96 _SFR96_ ; /* */ +sfr at 0x97 _SFR97_ ; /* */ +sfr at 0x98 S0CON ; /* UART 0 CONTROL */ +sfr at 0x99 _SFR99_ ; /* UART 0 BUFFER */ +sfr at 0x9A IEN2 ; /* SPI 0 CONFIGURATION */ +sfr at 0x9B S1CON ; /* SPI 0 DATA */ +sfr at 0x9C T2CT ; /* SPI 0 DATA */ +sfr at 0x9D T2PR ; /* SPI 0 CLOCK RATE CONTROL */ +sfr at 0x9E T2CTL ; /* SPI 0 CLOCK RATE CONTROL */ +sfr at 0x9F _SFR9F_ ; /* SPI 0 CLOCK RATE CONTROL */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA1 WORIRQ ; /* EMIF TIMING CONTROL */ +sfr at 0xA2 WORCTRL ; /* EMIF CONTROL */ +sfr at 0xA3 WOREVT0 ; /* EMIF CONFIGURATION */ +sfr at 0xA4 WOREVT1 ; /* EMIF CONFIGURATION */ +sfr at 0xA5 WORTIME0 ; /* EMIF CONFIGURATION */ +sfr at 0xA6 WORTIME1 ; /* EMIF CONFIGURATION */ +sfr at 0xA7 _SFRA7_ ; /* EMIF CONFIGURATION */ +sfr at 0xA8 IEN0 ; /* INTERRUPT ENABLE */ +sfr at 0xA9 IP0 ; /* UART 0 SLAVE ADDRESS */ +sfr at 0xAA _SFRAA_ ; /* */ +sfr at 0xAB FWT ; /* */ +sfr at 0xAC FADDRL ; /* */ +sfr at 0xAD FADDRH ; /* */ +sfr at 0xAE FCTL ; /* */ +sfr at 0xAF FWDATA ; /* */ +sfr at 0xB0 _SFRB0_ ; /* */ +sfr at 0xB1 ENCDI ; /* FLASH BANK SELECT */ +sfr at 0xB2 ENCDO ; /* */ +sfr at 0xB3 ENCCS ; /* */ +sfr at 0xB4 ADCCON1 ; /* */ +sfr at 0xB5 ADCCON2 ; /* */ +sfr at 0xB6 ADCCON3 ; /* */ +sfr at 0xB8 IEN1 ; /* INTERRUPT PRIORITY */ +sfr at 0xB9 IP1 ; /* */ +sfr at 0xBA ADCL ; /* */ +sfr at 0xBB ADCH ; /* */ +sfr at 0xBC RNDL ; /* */ +sfr at 0xBD RNDH ; /* */ +sfr at 0xBE SLEEP ; /* */ +sfr at 0xC0 IRCON ; /* */ +sfr at 0xC1 U0DBUF ; /* */ +sfr at 0xC2 U0BAUD ; /* */ +sfr at 0xC4 U0UCR ; /* */ +sfr at 0xC5 U0GCR ; /* */ +sfr at 0xC6 CLKCON ; /* */ +sfr at 0xC7 MEMCTR ; /* */ +sfr at 0xC9 WDCTL ; /* */ +sfr at 0xCA T3CNT ; /* */ +sfr at 0xCB T3CTL ; /* */ +sfr at 0xCC T3CCTL0 ; /* */ +sfr at 0xCD T3CC0 ; /* */ +sfr at 0xCE T3CCTL1 ; /* */ +sfr at 0xCF T3CC1 ; /* */ +sfr at 0xD0 PSW ; /* */ +sfr at 0xD1 DMAIRQ ; /* */ +sfr at 0xD2 DMA1CFGL ; /* */ +sfr at 0xD3 DMA1CFGH ; /* */ +sfr at 0xD4 DMA0CFGL ; /* */ +sfr at 0xD5 DMA0CFGH ; /* */ +sfr at 0xD6 DMAARM ; /* */ +sfr at 0xD7 DMAREQ ; /* */ +sfr at 0xD8 TIMIF ; /* */ +sfr at 0xD9 RFD ; /* */ +sfr at 0xDA T1CC0L ; /* */ +sfr at 0xDB T1CC0H ; /* */ +sfr at 0xDC T1CC1L ; /* */ +sfr at 0xDD T1CC1H ; /* */ +sfr at 0xDE T1CC2L ; /* */ +sfr at 0xDF T1CC2H ; /* */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE1 RFST ; /* */ +sfr at 0xE2 T1CNTL ; /* */ +sfr at 0xE3 T1CNTH ; /* */ +sfr at 0xE4 T1CTL ; /* */ +sfr at 0xE5 T1CCTL0 ; /* */ +sfr at 0xE6 T1CCTL1 ; /* */ +sfr at 0xE7 T1CCTL2 ; /* */ +sfr at 0xE8 IRCON2 ; /* */ +sfr at 0xE9 RFIF ; /* */ +sfr at 0xEA T4CNT ; /* */ +sfr at 0xEB T4CTL ; /* */ +sfr at 0xEC T4CCTL0 ; /* */ +sfr at 0xED T4CC0 ; /* */ +sfr at 0xEE T4CCTL1 ; /* */ +sfr at 0xEF T4CC1 ; /* */ +sfr at 0xF0 B ; /* */ +sfr at 0xF1 PERCFG ; /* */ +sfr at 0xF2 ADCCFG ; /* */ +sfr at 0xF3 P0SEL ; /* */ +sfr at 0xF4 P1SEL ; /* */ +sfr at 0xF5 P2SEL ; /* */ +sfr at 0xF6 P1INP ; /* */ +sfr at 0xF7 P2INP ; /* */ +sfr at 0xF8 U1CSR ; /* */ +sfr at 0xF9 U1DBUF ; /* */ +sfr at 0xFA U1BAUD ; /* */ +sfr at 0xFB U1UCR ; /* */ +sfr at 0xFC U1GCR ; /* */ +sfr at 0xFD P0DIR ; /* */ +sfr at 0xFE P1DIR ; /* */ +sfr at 0xFF P2DIR ; /* */ + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x89 RFTXRXIF; /* */ +sbit at 0x8B URX0IF ; /* */ +sbit at 0x8D ADCIF ; /* */ +sbit at 0x8F URX1IF ; /* */ +sbit at 0x8F I2SRXIF ; /* */ + +/* SCON0 0x98 */ +sbit at 0x98 ENCIF_0 ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x99 ENCIF_1 ; /* UART 0 RX INTERRUPT FLAG */ + +/* IEN0 0xA8 */ +sbit at 0xA8 RFTXRXIE; /* RF TX/RX done interrupt enable */ +sbit at 0xA9 ADCIE ; /* ADC interrupt enable */ +sbit at 0xAA URX0IE ; /* USART0 RX interrupt enable */ +sbit at 0xAB URX1IE ; /* USART1 RX interrupt enable */ +sbit at 0xAB I2SRXIE ; /* I2S RX interrupt enable */ +sbit at 0xAC ENCIE ; /* AES interrupt enable */ +sbit at 0xAD STIE ; /* Sleep Timer interrupt enable */ +sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ + +/* IEN1 0xB8 */ +sbit at 0xB8 DMAIE ; /* DMA transfer interrupt enable */ +sbit at 0xB9 T1IE ; /* Timer 1 interrupt enable */ +sbit at 0xBA T2IE ; /* Timer 2 interrupt enable */ +sbit at 0xBB T3IE ; /* Timer 3 interrupt enable */ +sbit at 0xBC T4IE ; /* Timer 4 interrupt enable */ +sbit at 0xBD P0IE ; /* Port 0 interrupt enable */ + +/* IRCON 0xC0 */ +sbit at 0xC0 DMAIF ; /* */ +sbit at 0xC1 T1IF ; /* */ +sbit at 0xC2 T2IF ; /* */ +sbit at 0xC3 T3IF ; /* */ +sbit at 0xC4 T4IF ; /* */ +sbit at 0xC5 P0IF ; /* */ +sbit at 0xC7 STIF ; /* */ + +/* PSW 0xD0 */ +sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* USER FLAG 1 */ +sbit at 0xD2 OV ; /* OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* USER FLAG 0 */ +sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* CARRY FLAG */ + +/* TIMIF D8H */ +sbit at 0xD8 T3OVFIF ; /* */ +sbit at 0xD9 T3CH0IF ; /* */ +sbit at 0xDA T3CH1IF ; /* */ +sbit at 0xDB T4OVFIF ; /* */ +sbit at 0xDC T4CH0IF ; /* */ +sbit at 0xDD T4CH1IF ; /* */ +sbit at 0xDE OVFIM ; /* */ + +/* IRCON2 E8H */ +sbit at 0xE8 P2IF ; /* */ +sbit at 0xE8 USBIF ; /* */ +sbit at 0xE9 UTX0IF ; /* */ +sbit at 0xEA UTX1IF ; /* */ +sbit at 0xEA I2STXIF ; /* */ +sbit at 0xEB P1IF ; /* */ +sbit at 0xEC WDTIF ; /* */ + +/* U1CSR F8H */ +sbit at 0xF8 U1_ACTIVE ; /* */ +sbit at 0xF9 U1_TX_BYTE ; /* */ +sbit at 0xFA U1_RX_BYTE ; /* */ +sbit at 0xFB U1_ERR ; /* */ +sbit at 0xFC U1_FE ; /* */ +sbit at 0xFD U1_SLAVE ; /* */ +sbit at 0xFE U1_RE ; /* */ +sbit at 0xFF U1_MODE ; /* */ + +#define T1CTL_MODE_SUSPENDED (0 << 0) +#define T1CTL_MODE_FREE (1 << 0) +#define T1CTL_MODE_MODULO (2 << 0) +#define T1CTL_MODE_UP_DOWN (3 << 0) +#define T1CTL_MODE_MASK (3 << 0) +#define T1CTL_DIV_1 (0 << 2) +#define T1CTL_DIV_8 (1 << 2) +#define T1CTL_DIV_32 (2 << 2) +#define T1CTL_DIV_128 (3 << 2) +#define T1CTL_DIV_MASK (3 << 2) +#define T1CTL_OVFIF (1 << 4) +#define T1CTL_CH0IF (1 << 5) +#define T1CTL_CH1IF (1 << 6) +#define T1CTL_CH2IF (1 << 7) + +#define T1CCTL_NO_CAPTURE (0 << 0) +#define T1CCTL_CAPTURE_RISING (1 << 0) +#define T1CCTL_CAPTURE_FALLING (2 << 0) +#define T1CCTL_CAPTURE_BOTH (3 << 0) +#define T1CCTL_CAPTURE_MASK (3 << 0) + +#define T1CCTL_MODE_CAPTURE (0 << 2) +#define T1CCTL_MODE_COMPARE (1 << 2) + +#define T1CTL_CMP_SET (0 << 3) +#define T1CTL_CMP_CLEAR (1 << 3) +#define T1CTL_CMP_TOGGLE (2 << 3) +#define T1CTL_CMP_SET_CLEAR (3 << 3) +#define T1CTL_CMP_CLEAR_SET (4 << 3) + +#define T1CTL_IM_DISABLED (0 << 6) +#define T1CTL_IM_ENABLED (1 << 6) + +#define T1CTL_CPSEL_NORMAL (0 << 7) +#define T1CTL_CPSEL_RF (1 << 7) + +#endif diff --git a/target/timer/timer.c b/target/timer/timer.c new file mode 100644 index 00000000..ae75d0a8 --- /dev/null +++ b/target/timer/timer.c @@ -0,0 +1,55 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include "cc1111.h" + +unsigned char irqs; + +void timer1_isr(void) interrupt 9 __reentrant +{ + ++irqs; + if (irqs == 100) { + P1 ^= 0x2; + irqs = 0; + } +} + +int +main (void) __reentrant +{ + CLKCON = 0; + P1DIR = 0x2; + P1 = 0xff; + + T1CTL = 0; + + /* 30000 */ + T1CC0H = 0x75; + T1CC0L = 0x30; + T1CCTL0 = T1CCTL_MODE_COMPARE; + T1CCTL1 = 0; + T1CCTL2 = 0; + + /* clear timer value */ + T1CNTL = 0; + OVFIM = 1; + T1CTL = T1CTL_MODE_MODULO | T1CTL_DIV_8; + T1IE = 1; + EA = 1; + for (;;); +} -- cgit v1.2.3 From eb09e61b0682eb2aeac8e1a34d58b897ba6db8e7 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Mon, 5 Jan 2009 21:44:44 -0800 Subject: Use custom sdcc libraries (this needs to be configured...) Signed-off-by: Keith Packard --- target/simple/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/simple/Makefile b/target/simple/Makefile index c4432325..70c0f888 100644 --- a/target/simple/Makefile +++ b/target/simple/Makefile @@ -7,7 +7,7 @@ CFLAGS=--model-large $(DEBUG) --less-pedantic \ --no-peep --int-long-reent --float-reent \ --data-loc 0x30 -LDFLAGS=-L/usr/share/sdcc/lib/large --out-fmt-ihx +LDFLAGS=-L/local/share/sdcc/lib/large --out-fmt-ihx LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf400 --xram-size 1024 LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 -- cgit v1.2.3 From 164b4e4749ad64ebbe26e84fd7b4fa1aa733dbe4 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Sun, 15 Mar 2009 18:11:20 -0700 Subject: sdcc gets the lib path correct based on the model --- target/blink/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/blink/Makefile b/target/blink/Makefile index 4c9b4102..d0112e62 100644 --- a/target/blink/Makefile +++ b/target/blink/Makefile @@ -7,7 +7,7 @@ CFLAGS=--model-large $(DEBUG) --less-pedantic \ --no-peep --int-long-reent --float-reent \ --data-loc 0x30 -LDFLAGS=-L/usr/share/sdcc/lib/large --out-fmt-ihx +LDFLAGS=--out-fmt-ihx LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf400 --xram-size 1024 LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 -- cgit v1.2.3 From 25b77d236c01258abfc03114c2fc9ea2d69ca6e7 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Sun, 15 Mar 2009 18:11:53 -0700 Subject: Add telemetrum beeper example --- target/beep/Makefile | 46 +++++++++++++++++++++++++++ target/beep/beep.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 135 insertions(+) create mode 100644 target/beep/Makefile create mode 100644 target/beep/beep.c (limited to 'target') diff --git a/target/beep/Makefile b/target/beep/Makefile new file mode 100644 index 00000000..8f600b4a --- /dev/null +++ b/target/beep/Makefile @@ -0,0 +1,46 @@ +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse \ + --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large $(DEBUG) --less-pedantic \ + --no-peep --int-long-reent --float-reent \ + --data-loc 0x30 + +LDFLAGS=--out-fmt-ihx +LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf400 --xram-size 1024 + +LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 + +SRC=beep.c +ADB=$(SRC:.c=.adb) +ASM=$(SRC:.c=.asm) +LNK=$(SRC:.c=.lnk) +LST=$(SRC:.c=.lst) +REL=$(SRC:.c=.rel) +RST=$(SRC:.c=.rst) +SYM=$(SRC:.c=.sym) + +PROGS=beep-flash.ihx beep-ram.ihx +PCDB=$(PROGS:.ihx=.cdb) +PLNK=$(PROGS:.ihx=.lnk) +PMAP=$(PROGS:.ihx=.map) +PMEM=$(PROGS:.ihx=.mem) +PAOM=$(PROGS:.ihx=) + +%.rel : %.c + $(CC) -c $(CFLAGS) -o$*.rel $< + +all: $(PROGS) + +beep-ram.ihx: $(REL) Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o beep-ram.ihx $(REL) + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o beep-flash.ihx $(REL) + +beep-flash.ihx: beep-ram.ihx + +clean: + rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) + rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) + +install: diff --git a/target/beep/beep.c b/target/beep/beep.c new file mode 100644 index 00000000..08422082 --- /dev/null +++ b/target/beep/beep.c @@ -0,0 +1,89 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +sfr at 0x80 P0; +sfr at 0x90 P1; +sfr at 0xA0 P2; +sfr at 0xC6 CLKCON; + +sfr at 0xF1 PERCFG; +sfr at 0xF2 ADCCFG; +sfr at 0xF3 P0SEL; +sfr at 0xF4 P1SEL; +sfr at 0xF5 P2SEL; + +sfr at 0xFD P0DIR; +sfr at 0xFE P1DIR; +sfr at 0xFF P2DIR; +sfr at 0x8F P0INP; +sfr at 0xF6 P1INP; +sfr at 0xF7 P2INP; + +sfr at 0x89 P0IFG; +sfr at 0x8A P1IFG; +sfr at 0x8B P2IFG; + +#define nop() _asm nop _endasm; + +void +delay (unsigned char n) +{ + unsigned char i = 0; + + n <<= 1; + while (--n != 0) + while (--i != 0) + nop(); +} + +void +tone (unsigned char n, unsigned char m) +{ + unsigned char i = 0; + while (--m != 0) { + while (--i != 0) { + P2 = 0xff; + delay(n); + P2 = 0xfe; + delay(n); + } + } +} + +void +high() { + tone(1, 2); +} + +void +low() { + tone(2, 1); +} + +main () +{ + CLKCON = 0; + /* Set p1_1 to output */ + P2DIR = 0x01; + P1INP = 0x00; + P2INP = 0x00; + for (;;) { + high(); + low(); + } +} -- cgit v1.2.3 From a0a27600ee2bf237e74eb83767a8d2e7c91df24f Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Sun, 15 Mar 2009 18:14:21 -0700 Subject: Correctly comment which bit the beep program uses --- target/beep/beep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/beep/beep.c b/target/beep/beep.c index 08422082..3dd31d54 100644 --- a/target/beep/beep.c +++ b/target/beep/beep.c @@ -78,7 +78,7 @@ low() { main () { CLKCON = 0; - /* Set p1_1 to output */ + /* Set P2_0 to output */ P2DIR = 0x01; P1INP = 0x00; P2INP = 0x00; -- cgit v1.2.3 From 4726317de811c20e8d6754762437b5c9cbb3a48c Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 18 Mar 2009 01:54:34 -0700 Subject: Add simple test program to light up the transmitter at 434.550MHz This starts a transmit sequence, but doesn't send any data so the transmitter just locks on. --- target/radio/Makefile | 46 +++++ target/radio/radio.c | 525 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 571 insertions(+) create mode 100644 target/radio/Makefile create mode 100644 target/radio/radio.c (limited to 'target') diff --git a/target/radio/Makefile b/target/radio/Makefile new file mode 100644 index 00000000..a26fa458 --- /dev/null +++ b/target/radio/Makefile @@ -0,0 +1,46 @@ +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse \ + --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large $(DEBUG) --less-pedantic \ + --no-peep --int-long-reent --float-reent \ + --data-loc 0x30 + +LDFLAGS=--out-fmt-ihx +LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf400 --xram-size 1024 + +LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 + +SRC=radio.c +ADB=$(SRC:.c=.adb) +ASM=$(SRC:.c=.asm) +LNK=$(SRC:.c=.lnk) +LST=$(SRC:.c=.lst) +REL=$(SRC:.c=.rel) +RST=$(SRC:.c=.rst) +SYM=$(SRC:.c=.sym) + +PROGS=radio-flash.ihx radio-ram.ihx +PCDB=$(PROGS:.ihx=.cdb) +PLNK=$(PROGS:.ihx=.lnk) +PMAP=$(PROGS:.ihx=.map) +PMEM=$(PROGS:.ihx=.mem) +PAOM=$(PROGS:.ihx=) + +%.rel : %.c + $(CC) -c $(CFLAGS) -o$*.rel $< + +all: $(PROGS) + +radio-ram.ihx: $(REL) Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o radio-ram.ihx $(REL) + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o radio-flash.ihx $(REL) + +radio-flash.ihx: radio-ram.ihx + +clean: + rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) + rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) + +install: diff --git a/target/radio/radio.c b/target/radio/radio.c new file mode 100644 index 00000000..9f10fccd --- /dev/null +++ b/target/radio/radio.c @@ -0,0 +1,525 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include + +sfr at 0x80 P0; +sfr at 0x90 P1; +sfr at 0xA0 P2; +sfr at 0xC6 CLKCON; + +sfr at 0xF1 PERCFG; +sfr at 0xF2 ADCCFG; +sfr at 0xF3 P0SEL; +sfr at 0xF4 P1SEL; +sfr at 0xF5 P2SEL; + +sfr at 0xFD P0DIR; +sfr at 0xFE P1DIR; +sfr at 0xFF P2DIR; +sfr at 0x8F P0INP; +sfr at 0xF6 P1INP; +sfr at 0xF7 P2INP; + +sfr at 0x89 P0IFG; +sfr at 0x8A P1IFG; +sfr at 0x8B P2IFG; + +sfr at 0xD9 RFD; +sfr at 0xE9 RFIF; +sfr at 0xE1 RFST; + +sfr at 0x88 TCON; + +sbit at 0x89 RFTXRXIF; + +#define TCON_RFTXRXIF (1 << 1) + +#define RFST_SFSTXON 0x00 +#define RFST_SCAL 0x01 +#define RFST_SRX 0x02 +#define RFST_STX 0x03 +#define RFST_SIDLE 0x04 + +__xdata __at (0xdf00) uint8_t RF[0x3c]; + +__xdata __at (0xdf2f) uint8_t RF_IOCFG2; +#define RF_IOCFG2_OFF 0x2f + +__xdata __at (0xdf30) uint8_t RF_IOCFG1; +#define RF_IOCFG1_OFF 0x30 + +__xdata __at (0xdf31) uint8_t RF_IOCFG0; +#define RF_IOCFG0_OFF 0x31 + +__xdata __at (0xdf00) uint8_t RF_SYNC1; +#define RF_SYNC1_OFF 0x00 + +__xdata __at (0xdf01) uint8_t RF_SYNC0; +#define RF_SYNC0_OFF 0x01 + +__xdata __at (0xdf02) uint8_t RF_PKTLEN; +#define RF_PKTLEN_OFF 0x02 + +__xdata __at (0xdf03) uint8_t RF_PKTCTRL1; +#define RF_PKTCTRL1_OFF 0x03 + +__xdata __at (0xdf04) uint8_t RF_PKTCTRL0; +#define RF_PKTCTRL0_OFF 0x04 + +__xdata __at (0xdf05) uint8_t RF_ADDR; +#define RF_ADDR_OFF 0x05 + +__xdata __at (0xdf06) uint8_t RF_CHANNR; +#define RF_CHANNR_OFF 0x06 + +__xdata __at (0xdf07) uint8_t RF_FSCTRL1; +#define RF_FSCTRL1_OFF 0x07 + +#define RF_FSCTRL1_FREQ_IF_SHIFT (0) + +__xdata __at (0xdf08) uint8_t RF_FSCTRL0; +#define RF_FSCTRL0_OFF 0x08 + +#define RF_FSCTRL0_FREQOFF_SHIFT (0) + +__xdata __at (0xdf09) uint8_t RF_FREQ2; +#define RF_FREQ2_OFF 0x09 + +__xdata __at (0xdf0a) uint8_t RF_FREQ1; +#define RF_FREQ1_OFF 0x0a + +__xdata __at (0xdf0b) uint8_t RF_FREQ0; +#define RF_FREQ0_OFF 0x0b + +__xdata __at (0xdf0c) uint8_t RF_MDMCFG4; +#define RF_MDMCFG4_OFF 0x0c + +#define RF_MDMCFG4_CHANBW_E_SHIFT 6 +#define RF_MDMCFG4_CHANBW_M_SHIFT 4 +#define RF_MDMCFG4_DRATE_E_SHIFT 0 + +__xdata __at (0xdf0d) uint8_t RF_MDMCFG3; +#define RF_MDMCFG3_OFF 0x0d + +#define RF_MDMCFG3_DRATE_M_SHIFT 0 + +__xdata __at (0xdf0e) uint8_t RF_MDMCFG2; +#define RF_MDMCFG2_OFF 0x0e + +#define RF_MDMCFG2_DEM_DCFILT_OFF (1 << 7) + +#define RF_MDMCFG2_MOD_FORMAT_MASK (7 << 4) +#define RF_MDMCFG2_MOD_FORMAT_2_FSK (0 << 4) +#define RF_MDMCFG2_MOD_FORMAT_GFSK (1 << 4) +#define RF_MDMCFG2_MOD_FORMAT_ASK_OOK (3 << 4) +#define RF_MDMCFG2_MOD_FORMAT_MSK (7 << 4) + +#define RF_MDMCFG2_MANCHESTER_EN (1 << 3) + +#define RF_MDMCFG2_SYNC_MODE_MASK (0x7 << 0) +#define RF_MDMCFG2_SYNC_MODE_NONE (0x0 << 0) +#define RF_MDMCFG2_SYNC_MODE_15_16 (0x1 << 0) +#define RF_MDMCFG2_SYNC_MODE_16_16 (0x2 << 0) +#define RF_MDMCFG2_SYNC_MODE_30_32 (0x3 << 0) +#define RF_MDMCFG2_SYNC_MODE_NONE_THRES (0x4 << 0) +#define RF_MDMCFG2_SYNC_MODE_15_16_THRES (0x5 << 0) +#define RF_MDMCFG2_SYNC_MODE_16_16_THRES (0x6 << 0) +#define RF_MDMCFG2_SYNC_MODE_30_32_THRES (0x7 << 0) + +__xdata __at (0xdf0f) uint8_t RF_MDMCFG1; +#define RF_MDMCFG1_OFF 0x0f + +#define RF_MDMCFG1_FEC_EN (1 << 7) + +#define RF_MDMCFG1_NUM_PREAMBLE_MASK (7 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_2 (0 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_3 (1 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_4 (2 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_6 (3 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_8 (4 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_12 (5 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_16 (6 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_24 (7 << 4) + +#define RF_MDMCFG1_CHANSPC_E_MASK (3 << 0) +#define RF_MDMCFG1_CHANSPC_E_SHIFT (0) + +__xdata __at (0xdf10) uint8_t RF_MDMCFG0; +#define RF_MDMCFG0_OFF 0x10 + +#define RF_MDMCFG0_CHANSPC_M_SHIFT (0) + +__xdata __at (0xdf11) uint8_t RF_DEVIATN; +#define RF_DEVIATN_OFF 0x11 + +#define RF_DEVIATN_DEVIATION_E_SHIFT 4 +#define RF_DEVIATN_DEVIATION_M_SHIFT 0 + +__xdata __at (0xdf12) uint8_t RF_MCSM2; +#define RF_MCSM2_OFF 0x12 + +__xdata __at (0xdf13) uint8_t RF_MCSM1; +#define RF_MCSM1_OFF 0x13 + +__xdata __at (0xdf14) uint8_t RF_MCSM0; +#define RF_MCSM0_OFF 0x14 + +__xdata __at (0xdf15) uint8_t RF_FOCCFG; +#define RF_FOCCFG_OFF 0x15 + +__xdata __at (0xdf16) uint8_t RF_BSCFG; +#define RF_BSCFG_OFF 0x16 + +__xdata __at (0xdf17) uint8_t RF_AGCCTRL2; +#define RF_AGCCTRL2_OFF 0x17 + +__xdata __at (0xdf18) uint8_t RF_AGCCTRL1; +#define RF_AGCCTRL1_OFF 0x18 + +__xdata __at (0xdf19) uint8_t RF_AGCCTRL0; +#define RF_AGCCTRL0_OFF 0x19 + +__xdata __at (0xdf1a) uint8_t RF_FREND1; +#define RF_FREND1_OFF 0x1a + +#define RF_FREND1_LNA_CURRENT_SHIFT 6 +#define RF_FREND1_LNA2MIX_CURRENT_SHIFT 4 +#define RF_FREND1_LODIV_BUF_CURRENT_RX_SHIFT 2 +#define RF_FREND1_MIX_CURRENT_SHIFT 0 + +__xdata __at (0xdf1b) uint8_t RF_FREND0; +#define RF_FREND0_OFF 0x1b + +#define RF_FREND0_LODIV_BUF_CURRENT_TX_MASK (0x3 << 4) +#define RF_FREND0_LODIV_BUF_CURRENT_TX_SHIFT 4 +#define RF_FREND0_PA_POWER_MASK (0x7) +#define RF_FREND0_PA_POWER_SHIFT 0 + +__xdata __at (0xdf1c) uint8_t RF_FSCAL3; +#define RF_FSCAL3_OFF 0x1c + +__xdata __at (0xdf1d) uint8_t RF_FSCAL2; +#define RF_FSCAL2_OFF 0x1d + +__xdata __at (0xdf1e) uint8_t RF_FSCAL1; +#define RF_FSCAL1_OFF 0x1e + +__xdata __at (0xdf1f) uint8_t RF_FSCAL0; +#define RF_FSCAL0_OFF 0x1f + +__xdata __at (0xdf23) uint8_t RF_TEST2; +#define RF_TEST2_OFF 0x23 + +#define RF_TEST2_NORMAL_MAGIC 0x88 +#define RF_TEST2_RX_LOW_DATA_RATE_MAGIC 0x81 + +__xdata __at (0xdf24) uint8_t RF_TEST1; +#define RF_TEST1_OFF 0x24 + +#define RF_TEST1_TX_MAGIC 0x31 +#define RF_TEST1_RX_LOW_DATA_RATE_MAGIC 0x35 + +__xdata __at (0xdf25) uint8_t RF_TEST0; +#define RF_TEST0_OFF 0x25 + +#define RF_TEST0_7_2_MASK (0xfc) +#define RF_TEST0_VCO_SEL_CAL_EN (1 << 1) +#define RF_TEST0_0_MASK (1) + +/* These are undocumented, and must be computed + * using the provided tool. + */ +__xdata __at (0xdf27) uint8_t RF_PA_TABLE7; +#define RF_PA_TABLE7_OFF 0x27 + +__xdata __at (0xdf28) uint8_t RF_PA_TABLE6; +#define RF_PA_TABLE6_OFF 0x28 + +__xdata __at (0xdf29) uint8_t RF_PA_TABLE5; +#define RF_PA_TABLE5_OFF 0x29 + +__xdata __at (0xdf2a) uint8_t RF_PA_TABLE4; +#define RF_PA_TABLE4_OFF 0x2a + +__xdata __at (0xdf2b) uint8_t RF_PA_TABLE3; +#define RF_PA_TABLE3_OFF 0x2b + +__xdata __at (0xdf2c) uint8_t RF_PA_TABLE2; +#define RF_PA_TABLE2_OFF 0x2c + +__xdata __at (0xdf2d) uint8_t RF_PA_TABLE1; +#define RF_PA_TABLE1_OFF 0x2d + +__xdata __at (0xdf2e) uint8_t RF_PA_TABLE0; +#define RF_PA_TABLE0_OFF 0x2e + +__xdata __at (0xdf36) uint8_t RF_PARTNUM; +#define RF_PARTNUM_OFF 0x36 + +__xdata __at (0xdf37) uint8_t RF_VERSION; +#define RF_VERSION_OFF 0x37 + +__xdata __at (0xdf38) uint8_t RF_FREQEST; +#define RF_FREQEST_OFF 0x38 + +__xdata __at (0xdf39) uint8_t RF_LQI; +#define RF_LQI_OFF 0x39 + +#define RF_LQI_CRC_OK (1 << 7) +#define RF_LQI_LQI_EST_MASK (0x7f) + +__xdata __at (0xdf3a) uint8_t RF_RSSI; +#define RF_RSSI_OFF 0x3a + +__xdata __at (0xdf3b) uint8_t RF_MARCSTATE; +#define RF_MARCSTATE_OFF 0x3b + +#define RF_MARCSTATE_MASK 0x0f +#define RF_MARCSTATE_SLEEP 0x00 +#define RF_MARCSTATE_IDLE 0x01 +#define RF_MARCSTATE_VCOON_MC 0x03 +#define RF_MARCSTATE_REGON_MC 0x04 +#define RF_MARCSTATE_MANCAL 0x05 +#define RF_MARCSTATE_VCOON 0x06 +#define RF_MARCSTATE_REGON 0x07 +#define RF_MARCSTATE_STARTCAL 0x08 +#define RF_MARCSTATE_BWBOOST 0x09 +#define RF_MARCSTATE_FS_LOCK 0x0a +#define RF_MARCSTATE_IFADCON 0x0b +#define RF_MARCSTATE_ENDCAL 0x0c +#define RF_MARCSTATE_RX 0x0d +#define RF_MARCSTATE_RX_END 0x0e +#define RF_MARCSTATE_RX_RST 0x0f +#define RF_MARCSTATE_TXRX_SWITCH 0x10 +#define RF_MARCSTATE_RX_OVERFLOW 0x11 +#define RF_MARCSTATE_FSTXON 0x12 +#define RF_MARCSTATE_TX 0x13 +#define RF_MARCSTATE_TX_END 0x14 +#define RF_MARCSTATE_RXTX_SWITCH 0x15 +#define RF_MARCSTATE_TX_UNDERFLOW 0x16 + + +__xdata __at (0xdf3c) uint8_t RF_PKTSTATUS; +#define RF_PKTSTATUS_OFF 0x3c + +#define RF_PKTSTATUS_CRC_OK (1 << 7) +#define RF_PKTSTATUS_CS (1 << 6) +#define RF_PKTSTATUS_PQT_REACHED (1 << 5) +#define RF_PKTSTATUS_CCA (1 << 4) +#define RF_PKTSTATUS_SFD (1 << 3) + +__xdata __at (0xdf3d) uint8_t RF_VCO_VC_DAC; +#define RF_VCO_VC_DAC_OFF 0x3d + +#define nop() _asm nop _endasm; + +void +delay (unsigned char n) +{ + unsigned char i = 0; + + n <<= 1; + while (--n != 0) + while (--i != 0) + nop(); +} + +void +tone (unsigned char n, unsigned char m) +{ + unsigned char i = 0; + while (--m != 0) { + i = 128; + while (--i != 0) { + P2 = 0xff; + delay(n); + P2 = 0xfe; + delay(n); + } + } +} + +void +high() { + tone(1, 2); +} + +void +low() { + tone(2, 1); +} + +/* Values from SmartRF® Studio for: + * + * Deviation: 20.507812 kHz + * Datarate: 38.360596 kBaud + * Modulation: GFSK + * RF Freq: 434.549927 MHz + * Channel: 99.975586 kHz + * Channel: 0 + * RX filter: 93.75 kHz + */ + +/* + * For 434.550MHz, the frequency value is: + * + * 434.550e6 / (24e6 / 2**16) = 1186611.2 + */ + +#define FREQ_CONTROL 1186611 + +/* + * For IF freq of 140.62kHz, the IF value is: + * + * 140.62e3 / (24e6 / 2**10) = 6 + */ + +#define IF_FREQ_CONTROL 6 + +/* + * For channel bandwidth of 93.75 kHz, the CHANBW_E and CHANBW_M values are + * + * BW = 24e6 / (8 * (4 + M) * 2 ** E) + * + * So, M = 0 and E = 3 + */ + +#define CHANBW_M 0 +#define CHANBW_E 3 + +/* + * For a symbol rate of 38360kBaud, the DRATE_E and DRATE_M values are: + * + * R = (256 + M) * 2** E * 24e6 / 2**28 + * + * So M is 163 and E is 10 + */ + +#define DRATE_E 10 +#define DRATE_M 163 + +#define PACKET_LEN 128 + +static __code uint8_t radio_setup[] = { + RF_PA_TABLE7_OFF, 0x60, + RF_PA_TABLE6_OFF, 0x60, + RF_PA_TABLE5_OFF, 0x60, + RF_PA_TABLE4_OFF, 0x60, + RF_PA_TABLE3_OFF, 0x60, + RF_PA_TABLE2_OFF, 0x60, + RF_PA_TABLE1_OFF, 0x60, + RF_PA_TABLE0_OFF, 0x60, + + RF_FREQ2_OFF, FREQ_CONTROL >> 16, + RF_FREQ1_OFF, FREQ_CONTROL >> 8, + RF_FREQ0_OFF, FREQ_CONTROL >> 0, + + RF_FSCTRL1_OFF, (IF_FREQ_CONTROL << RF_FSCTRL1_FREQ_IF_SHIFT), + RF_FSCTRL0_OFF, (0 << RF_FSCTRL0_FREQOFF_SHIFT), + + RF_MDMCFG4_OFF, ((CHANBW_E << RF_MDMCFG4_CHANBW_E_SHIFT) | + (CHANBW_M << RF_MDMCFG4_CHANBW_M_SHIFT) | + (DRATE_E << RF_MDMCFG4_DRATE_E_SHIFT)), + RF_MDMCFG3_OFF, (DRATE_M << RF_MDMCFG3_DRATE_M_SHIFT), + RF_MDMCFG2_OFF, (RF_MDMCFG2_DEM_DCFILT_OFF | + RF_MDMCFG2_MOD_FORMAT_GFSK | + RF_MDMCFG2_SYNC_MODE_NONE), + RF_MDMCFG1_OFF, (RF_MDMCFG1_NUM_PREAMBLE_4 | + (2 << RF_MDMCFG1_CHANSPC_E_SHIFT)), + RF_MDMCFG0_OFF, (17 << RF_MDMCFG0_CHANSPC_M_SHIFT), + + RF_CHANNR_OFF, 0, + + RF_DEVIATN_OFF, ((3 << RF_DEVIATN_DEVIATION_E_SHIFT) | + (6 << RF_DEVIATN_DEVIATION_M_SHIFT)), + + /* SmartRF says set LODIV_BUF_CURRENT_TX to 0 + * And, we're not using power ramping, so use PA_POWER 0 + */ + RF_FREND0_OFF, ((1 << RF_FREND0_LODIV_BUF_CURRENT_TX_SHIFT) | + (0 << RF_FREND0_PA_POWER_SHIFT)), + + RF_FREND1_OFF, ((1 << RF_FREND1_LNA_CURRENT_SHIFT) | + (1 << RF_FREND1_LNA2MIX_CURRENT_SHIFT) | + (1 << RF_FREND1_LODIV_BUF_CURRENT_RX_SHIFT) | + (2 << RF_FREND1_MIX_CURRENT_SHIFT)), + RF_MCSM0_OFF, 0x18, + RF_FOCCFG_OFF, 0x16, + RF_BSCFG_OFF, 0x6C, + + RF_AGCCTRL2_OFF, 0x43, + RF_AGCCTRL1_OFF, 0x40, + RF_AGCCTRL0_OFF, 0x91, + + RF_FSCAL3_OFF, 0xE9, + RF_FSCAL2_OFF, 0x0A, + RF_FSCAL1_OFF, 0x00, + RF_FSCAL0_OFF, 0x1F, + + RF_TEST2_OFF, 0x88, + RF_TEST1_OFF, 0x31, + RF_TEST0_OFF, 0x09, + + /* default sync values */ + RF_SYNC1_OFF, 0xD3, + RF_SYNC0_OFF, 0x91, + + /* max packet length */ + RF_PKTLEN_OFF, PACKET_LEN, + + RF_PKTCTRL1_OFF, 0x04, + RF_PKTCTRL0_OFF, 0x00, + RF_ADDR_OFF, 0x00, + RF_MCSM2_OFF, 0x07, + RF_MCSM1_OFF, 0x30, + + RF_IOCFG2_OFF, 0x00, + RF_IOCFG1_OFF, 0x00, + RF_IOCFG0_OFF, 0x00, +}; + +void +radio_init() { + uint8_t i; + for (i = 0; i < sizeof (radio_setup); i += 2) + RF[radio_setup[i]] = radio_setup[i+1]; +} + +main () +{ + CLKCON = 0; + /* Set P2_0 to output */ + radio_init (); + delay(100); + RFST = RFST_SIDLE; + delay(100); + RFST = RFST_STX; + delay(100); + for (;;); +#if 0 + for (;;) { + uint8_t i; + for (i = 0; i < PACKET_LEN; i++) { + while (!RFTXRXIF); + RFTXRXIF = 0; + RFD = 0x55; + } + } +#endif +} -- cgit v1.2.3 From 6eeee64cf16ccc9218dbdde5426f25bda5e3407f Mon Sep 17 00:00:00 2001 From: Bdale Garbee Date: Wed, 18 Mar 2009 02:58:33 -0600 Subject: working beep at around 4khz --- COPYING | 7 +++--- INSTALL | 69 ++++++++++++++++++++++++------------------------------ Makefile.am | 2 +- target/beep/beep.c | 6 +++-- 4 files changed, 39 insertions(+), 45 deletions(-) (limited to 'target') diff --git a/COPYING b/COPYING index 10828e06..d60c31a9 100644 --- a/COPYING +++ b/COPYING @@ -1,9 +1,8 @@ - GNU GENERAL PUBLIC LICENSE Version 2, June 1991 Copyright (C) 1989, 1991 Free Software Foundation, Inc. - 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. @@ -306,7 +305,7 @@ the "copyright" line and a pointer to where the full notice is found. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Also add information on how to contact you by electronic and paper mail. @@ -314,7 +313,7 @@ Also add information on how to contact you by electronic and paper mail. If the program is interactive, make it output a short notice like this when it starts in an interactive mode: - Gnomovision version 69, Copyright (C) year name of author + Gnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. diff --git a/INSTALL b/INSTALL index 23e5f25d..54caf7c1 100644 --- a/INSTALL +++ b/INSTALL @@ -1,16 +1,13 @@ -Installation Instructions -************************* +Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002 Free Software +Foundation, Inc. -Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002, 2004, 2005 Free -Software Foundation, Inc. - -This file is free documentation; the Free Software Foundation gives + This file is free documentation; the Free Software Foundation gives unlimited permission to copy, distribute and modify it. Basic Installation ================== -These are generic installation instructions. + These are generic installation instructions. The `configure' shell script attempts to guess correct values for various system-dependent variables used during compilation. It uses @@ -70,9 +67,9 @@ The simplest way to compile this package is: Compilers and Options ===================== -Some systems require unusual options for compilation or linking that the -`configure' script does not know about. Run `./configure --help' for -details on some of the pertinent environment variables. + Some systems require unusual options for compilation or linking that +the `configure' script does not know about. Run `./configure --help' +for details on some of the pertinent environment variables. You can give `configure' initial values for configuration parameters by setting variables in the command line or in the environment. Here @@ -85,7 +82,7 @@ is an example: Compiling For Multiple Architectures ==================================== -You can compile the package for more than one kind of computer at the + You can compile the package for more than one kind of computer at the same time, by placing the object files for each architecture in their own directory. To do this, you must use a version of `make' that supports the `VPATH' variable, such as GNU `make'. `cd' to the @@ -102,19 +99,19 @@ for another architecture. Installation Names ================== -By default, `make install' installs the package's commands under -`/usr/local/bin', include files under `/usr/local/include', etc. You -can specify an installation prefix other than `/usr/local' by giving -`configure' the option `--prefix=PREFIX'. + By default, `make install' will install the package's files in +`/usr/local/bin', `/usr/local/man', etc. You can specify an +installation prefix other than `/usr/local' by giving `configure' the +option `--prefix=PATH'. You can specify separate installation prefixes for architecture-specific files and architecture-independent files. If you -pass the option `--exec-prefix=PREFIX' to `configure', the package uses -PREFIX as the prefix for installing programs and libraries. -Documentation and other data files still use the regular prefix. +give `configure' the option `--exec-prefix=PATH', the package will use +PATH as the prefix for installing programs and libraries. +Documentation and other data files will still use the regular prefix. In addition, if you use an unusual directory layout you can give -options like `--bindir=DIR' to specify different values for particular +options like `--bindir=PATH' to specify different values for particular kinds of files. Run `configure --help' for a list of the directories you can set and what kinds of files go in them. @@ -125,7 +122,7 @@ option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'. Optional Features ================= -Some packages pay attention to `--enable-FEATURE' options to + Some packages pay attention to `--enable-FEATURE' options to `configure', where FEATURE indicates an optional part of the package. They may also pay attention to `--with-PACKAGE' options, where PACKAGE is something like `gnu-as' or `x' (for the X Window System). The @@ -140,11 +137,11 @@ you can use the `configure' options `--x-includes=DIR' and Specifying the System Type ========================== -There may be some features `configure' cannot figure out automatically, -but needs to determine by the type of machine the package will run on. -Usually, assuming the package is built to be run on the _same_ -architectures, `configure' can figure that out, but if it prints a -message saying it cannot guess the machine type, give it the + There may be some features `configure' cannot figure out +automatically, but needs to determine by the type of machine the package +will run on. Usually, assuming the package is built to be run on the +_same_ architectures, `configure' can figure that out, but if it prints +a message saying it cannot guess the machine type, give it the `--build=TYPE' option. TYPE can either be a short name for the system type, such as `sun4', or a canonical name which has the form: @@ -159,7 +156,7 @@ where SYSTEM can have one of these forms: need to know the machine type. If you are _building_ compiler tools for cross-compiling, you should -use the option `--target=TYPE' to select the type of system they will +use the `--target=TYPE' option to select the type of system they will produce code for. If you want to _use_ a cross compiler, that generates code for a @@ -170,9 +167,9 @@ eventually be run) with `--host=TYPE'. Sharing Defaults ================ -If you want to set default values for `configure' scripts to share, you -can create a site shell script called `config.site' that gives default -values for variables like `CC', `cache_file', and `prefix'. + If you want to set default values for `configure' scripts to share, +you can create a site shell script called `config.site' that gives +default values for variables like `CC', `cache_file', and `prefix'. `configure' looks for `PREFIX/share/config.site' if it exists, then `PREFIX/etc/config.site' if it exists. Or, you can set the `CONFIG_SITE' environment variable to the location of the site script. @@ -181,7 +178,7 @@ A warning: not all `configure' scripts look for a site script. Defining Variables ================== -Variables not defined in a site shell script can be set in the + Variables not defined in a site shell script can be set in the environment passed to `configure'. However, some packages may run configure again during the build, and the customized values of these variables may be lost. In order to avoid this problem, you should set @@ -189,18 +186,14 @@ them in the `configure' command line, using `VAR=value'. For example: ./configure CC=/usr/local2/bin/gcc -causes the specified `gcc' to be used as the C compiler (unless it is -overridden in the site shell script). Here is a another example: - - /bin/bash ./configure CONFIG_SHELL=/bin/bash - -Here the `CONFIG_SHELL=/bin/bash' operand causes subsequent -configuration-related scripts to be executed by `/bin/bash'. +will cause the specified gcc to be used as the C compiler (unless it is +overridden in the site shell script). `configure' Invocation ====================== -`configure' recognizes the following options to control how it operates. + `configure' recognizes the following options to control how it +operates. `--help' `-h' diff --git a/Makefile.am b/Makefile.am index 8a061ab7..5341ab33 100644 --- a/Makefile.am +++ b/Makefile.am @@ -1 +1 @@ -SUBDIRS=lib ccload s51 ccmanual target/blink +SUBDIRS=lib ccload s51 ccmanual diff --git a/target/beep/beep.c b/target/beep/beep.c index 3dd31d54..09c915b7 100644 --- a/target/beep/beep.c +++ b/target/beep/beep.c @@ -46,9 +46,11 @@ delay (unsigned char n) unsigned char i = 0; n <<= 1; - while (--n != 0) + while (--n != 0) { + i = 211; while (--i != 0) nop(); + } } void @@ -84,6 +86,6 @@ main () P2INP = 0x00; for (;;) { high(); - low(); +/* low(); */ } } -- cgit v1.2.3 From f0c233f25a208a636833312b1766825815735304 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 15:41:55 -0700 Subject: Add bit-banging spi eeprom test program --- target/ee/Makefile | 46 +++++++++++ target/ee/ee.c | 235 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 281 insertions(+) create mode 100644 target/ee/Makefile create mode 100644 target/ee/ee.c (limited to 'target') diff --git a/target/ee/Makefile b/target/ee/Makefile new file mode 100644 index 00000000..4c9abd1f --- /dev/null +++ b/target/ee/Makefile @@ -0,0 +1,46 @@ +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse \ + --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large $(DEBUG) --less-pedantic \ + --no-peep --int-long-reent --float-reent \ + --data-loc 0x30 + +LDFLAGS=--out-fmt-ihx +LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf800 --xram-size 1024 + +LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 + +SRC=ee.c +ADB=$(SRC:.c=.adb) +ASM=$(SRC:.c=.asm) +LNK=$(SRC:.c=.lnk) +LST=$(SRC:.c=.lst) +REL=$(SRC:.c=.rel) +RST=$(SRC:.c=.rst) +SYM=$(SRC:.c=.sym) + +PROGS=ee-flash.ihx ee-ram.ihx +PCDB=$(PROGS:.ihx=.cdb) +PLNK=$(PROGS:.ihx=.lnk) +PMAP=$(PROGS:.ihx=.map) +PMEM=$(PROGS:.ihx=.mem) +PAOM=$(PROGS:.ihx=) + +%.rel : %.c + $(CC) -c $(CFLAGS) -o$*.rel $< + +all: $(PROGS) + +ee-ram.ihx: $(REL) Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o ee-ram.ihx $(REL) + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o ee-flash.ihx $(REL) + +ee-flash.ihx: ee-ram.ihx + +clean: + rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) + rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) + +install: diff --git a/target/ee/ee.c b/target/ee/ee.c new file mode 100644 index 00000000..ab1b54e3 --- /dev/null +++ b/target/ee/ee.c @@ -0,0 +1,235 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include + +sfr at 0x80 P0; +sfr at 0x90 P1; +sfr at 0xA0 P2; +sfr at 0xC6 CLKCON; + +sfr at 0xF1 PERCFG; +sfr at 0xF2 ADCCFG; +sfr at 0xF3 P0SEL; +sfr at 0xF4 P1SEL; +sfr at 0xF5 P2SEL; + +sfr at 0xFD P0DIR; +sfr at 0xFE P1DIR; +sfr at 0xFF P2DIR; +sfr at 0x8F P0INP; +sfr at 0xF6 P1INP; +sfr at 0xF7 P2INP; + +sfr at 0x89 P0IFG; +sfr at 0x8A P1IFG; +sfr at 0x8B P2IFG; + +sbit at 0x90 P1_0; +sbit at 0x91 P1_1; +sbit at 0x92 P1_2; +sbit at 0x93 P1_3; +sbit at 0x94 P1_4; +sbit at 0x95 P1_5; +sbit at 0x96 P1_6; +sbit at 0x97 P1_7; + +#define MOSI P1_5 +#define MISO P1_4 +#define SCK P1_3 +#define CS P1_2 + +#define DEBUG P1_1 + +#define nop() _asm nop _endasm; + +void +delay (unsigned char n) +{ + unsigned char i = 0; + unsigned char j = 0; + + while (--n != 0) + while (--i != 0) + while (--j != 0) + nop(); +} + +void +cs(uint8_t b) +{ + CS = b; + delay(1); +} + +void +out_bit(uint8_t b) +{ + MOSI = b; + SCK = 1; + delay(1); + SCK = 0; + delay(1); +} + +void +out_byte(uint8_t byte) +{ + uint8_t s; + + for (s = 0; s < 8; s++) { + uint8_t b = (byte & 0x80) ? 1 : 0; + out_bit(b); + byte <<= 1; + } +} + +uint8_t +in_bit(void) +{ + uint8_t b; + SCK = 1; + delay(1); + b = MISO; + SCK = 0; + delay(1); + return b; +} + +uint8_t +in_byte(void) +{ + uint8_t byte = 0; + uint8_t s; + uint8_t b; + + for (s = 0; s < 8; s++) { + b = in_bit(); + byte = byte << 1; + byte |= s; + } + return byte; +} + +uint8_t +rdsr(void) +{ + uint8_t status; + cs(0); + out_byte(0x05); + status = in_byte(); + cs(1); + return status; +} + +void +wrsr(uint8_t status) +{ + cs(0); + out_byte(0x01); + out_byte(status); + cs(1); +} + +void +wren(void) +{ + cs(0); + out_byte(0x06); + cs(1); +} + +void +write(uint32_t addr, uint8_t *bytes, uint16_t len) +{ + wren(); + cs(0); + out_byte(0x02); + out_byte(addr >> 16); + out_byte(addr >> 8); + out_byte(addr); + while (len-- > 0) + out_byte(*bytes++); + cs(1); + for (;;) { + uint8_t status = rdsr(); + if ((status & (1 << 0)) == 0) + break; + } +} + +void +read(uint32_t addr, uint8_t *bytes, uint16_t len) +{ + cs(0); + out_byte(0x03); + out_byte(addr >> 16); + out_byte(addr >> 8); + out_byte(addr); + while (len-- > 0) + *bytes++ = in_byte(); + cs(1); +} + +void +debug_byte(uint8_t byte) +{ + uint8_t s; + + for (s = 0; s < 8; s++) { + DEBUG = byte & 1; + delay(2); + byte >>= 1; + } +} + +#define STRING "hi" +#define LENGTH 2 + +main () +{ + uint8_t status; + uint8_t buf[LENGTH]; + int i; + + CLKCON = 0; + + CS = 1; + SCK = 0; + P1DIR = ((1 << 5) | + (1 << 4) | + (1 << 3) | + (1 << 2) | + (1 << 1)); + status = rdsr(); + /* + * Turn off both block-protect bits + */ + status &= ~((1 << 3) | (1 << 2)); + /* + * Turn off write protect enable + */ + status &= ~(1 << 7); + wrsr(status); + write(0x0, STRING, LENGTH); + for (;;) { + read(0x0, buf, LENGTH); + for (i = 0; i < LENGTH; i++) + debug_byte(buf[i]); + } +} -- cgit v1.2.3 From fedd18b28ea54e1dabcd2f9e8cab3ae4ee0fd070 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 16:35:13 -0700 Subject: MISO needs to be an input --- target/ee/ee.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/ee/ee.c b/target/ee/ee.c index ab1b54e3..221d5979 100644 --- a/target/ee/ee.c +++ b/target/ee/ee.c @@ -212,7 +212,7 @@ main () CS = 1; SCK = 0; P1DIR = ((1 << 5) | - (1 << 4) | + (0 << 4) | (1 << 3) | (1 << 2) | (1 << 1)); -- cgit v1.2.3 From 3429016d1359ec650993d2fb0596184e3f717871 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 17:04:45 -0700 Subject: Adjust clock/data phase for spi test --- target/ee/ee.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'target') diff --git a/target/ee/ee.c b/target/ee/ee.c index 221d5979..83dd57eb 100644 --- a/target/ee/ee.c +++ b/target/ee/ee.c @@ -73,6 +73,7 @@ delay (unsigned char n) void cs(uint8_t b) { + SCK = 0; CS = b; delay(1); } @@ -81,10 +82,10 @@ void out_bit(uint8_t b) { MOSI = b; + delay(1); SCK = 1; delay(1); SCK = 0; - delay(1); } void @@ -103,11 +104,12 @@ uint8_t in_bit(void) { uint8_t b; + + delay(1); SCK = 1; delay(1); b = MISO; SCK = 0; - delay(1); return b; } -- cgit v1.2.3 From 8131389ee5018c05b721146a98367150cf500fdf Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 17:15:09 -0700 Subject: Oops, not merging in the bit read for SPI test --- target/ee/ee.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/ee/ee.c b/target/ee/ee.c index 83dd57eb..f105388b 100644 --- a/target/ee/ee.c +++ b/target/ee/ee.c @@ -123,7 +123,7 @@ in_byte(void) for (s = 0; s < 8; s++) { b = in_bit(); byte = byte << 1; - byte |= s; + byte |= b; } return byte; } -- cgit v1.2.3 From ef0eef68280e9b6ca5e3bb71062e23054340e1ed Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 17:22:36 -0700 Subject: Change spi test string --- target/ee/ee.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/ee/ee.c b/target/ee/ee.c index f105388b..2ad040ab 100644 --- a/target/ee/ee.c +++ b/target/ee/ee.c @@ -200,7 +200,7 @@ debug_byte(uint8_t byte) } } -#define STRING "hi" +#define STRING "\360\252" #define LENGTH 2 main () -- cgit v1.2.3 From 7de3a43887485c3c6cf52960376ccde33fb33985 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 19:54:02 -0700 Subject: Add USART-based SPI test code --- target/ee/ee.c | 245 +++++++++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 203 insertions(+), 42 deletions(-) (limited to 'target') diff --git a/target/ee/ee.c b/target/ee/ee.c index 2ad040ab..68b6e4cc 100644 --- a/target/ee/ee.c +++ b/target/ee/ee.c @@ -18,12 +18,31 @@ #include +/* + * Validate the SPI-connected EEPROM + */ + sfr at 0x80 P0; sfr at 0x90 P1; sfr at 0xA0 P2; sfr at 0xC6 CLKCON; sfr at 0xF1 PERCFG; +#define PERCFG_T1CFG_ALT_1 (0 << 6) +#define PERCFG_T1CFG_ALT_2 (1 << 6) + +#define PERCFG_T3CFG_ALT_1 (0 << 5) +#define PERCFG_T3CFG_ALT_2 (1 << 5) + +#define PERCFG_T4CFG_ALT_1 (0 << 4) +#define PERCFG_T4CFG_ALT_2 (1 << 4) + +#define PERCFG_U1CFG_ALT_1 (0 << 1) +#define PERCFG_U1CFG_ALT_2 (1 << 1) + +#define PERCFG_U0CFG_ALT_1 (0 << 0) +#define PERCFG_U0CFG_ALT_2 (1 << 0) + sfr at 0xF2 ADCCFG; sfr at 0xF3 P0SEL; sfr at 0xF4 P1SEL; @@ -49,6 +68,44 @@ sbit at 0x95 P1_5; sbit at 0x96 P1_6; sbit at 0x97 P1_7; +/* + * UART registers + */ + +sfr at 0x86 U0CSR; +sfr at 0xF8 U1CSR; + +# define UxCSR_MODE_UART (1 << 7) +# define UxCSR_MODE_SPI (0 << 7) +# define UxCSR_RE (1 << 6) +# define UxCSR_SLAVE (1 << 5) +# define UxCSR_MASTER (0 << 5) +# define UxCSR_FE (1 << 4) +# define UxCSR_ERR (1 << 3) +# define UxCSR_RX_BYTE (1 << 2) +# define UxCSR_TX_BYTE (1 << 1) +# define UxCSR_ACTIVE (1 << 0) + +sfr at 0xc4 U0UCR; +sfr at 0xfb U1UCR; + +sfr at 0xc5 U0GCR; +sfr at 0xfc U1GCR; + +# define UxGCR_CPOL_NEGATIVE (0 << 7) +# define UxGCR_CPOL_POSITIVE (1 << 7) +# define UxGCR_CPHA_FIRST_EDGE (0 << 6) +# define UxGCR_CPHA_SECOND_EDGE (1 << 6) +# define UxGCR_ORDER_LSB (0 << 5) +# define UxGCR_ORDER_MSB (1 << 5) +# define UxGCR_BAUD_E_MASK (0x1f) +# define UxGCR_BAUD_E_SHIFT 0 + +sfr at 0xc1 U0DBUF; +sfr at 0xf9 U1DBUF; +sfr at 0xc2 U0BAUD; +sfr at 0xfa U1BAUD; + #define MOSI P1_5 #define MISO P1_4 #define SCK P1_3 @@ -56,6 +113,9 @@ sbit at 0x97 P1_7; #define DEBUG P1_1 +#define BITBANG 0 +#define USART 1 + #define nop() _asm nop _endasm; void @@ -70,8 +130,14 @@ delay (unsigned char n) nop(); } +#if BITBANG + +/* + * This version directly manipulates the GPIOs to synthesize SPI + */ + void -cs(uint8_t b) +bitbang_cs(uint8_t b) { SCK = 0; CS = b; @@ -79,7 +145,7 @@ cs(uint8_t b) } void -out_bit(uint8_t b) +bitbang_out_bit(uint8_t b) { MOSI = b; delay(1); @@ -89,19 +155,19 @@ out_bit(uint8_t b) } void -out_byte(uint8_t byte) +bitbang_out_byte(uint8_t byte) { uint8_t s; for (s = 0; s < 8; s++) { uint8_t b = (byte & 0x80) ? 1 : 0; - out_bit(b); + bitbang_out_bit(b); byte <<= 1; } } uint8_t -in_bit(void) +bitbang_in_bit(void) { uint8_t b; @@ -114,60 +180,160 @@ in_bit(void) } uint8_t -in_byte(void) +bitbang_in_byte(void) { uint8_t byte = 0; uint8_t s; uint8_t b; for (s = 0; s < 8; s++) { - b = in_bit(); + b = bitbang_in_bit(); byte = byte << 1; byte |= b; } return byte; } +void +bit_bang_init(void) +{ + CS = 1; + SCK = 0; + P1DIR = ((1 << 5) | + (0 << 4) | + (1 << 3) | + (1 << 2) | + (1 << 1)); +} + +#define spi_init() bitbang_init() +#define spi_out_byte(b) bitbang_out_byte(b) +#define spi_in_byte() bitbang_in_byte() +#define spi_cs(b) bitbang_cs(b) +#endif + +#if USART + +/* + * This version uses the USART in SPI mode + */ +void +usart_init(void) +{ + /* + * Configure our chip select line + */ + CS = 1; + P1DIR |= (1 << 2); + /* + * Configure the peripheral pin choices + * for both of the serial ports + * + * Note that telemetrum will use U1CFG_ALT_2 + * but that overlaps with SPI ALT_2, so until + * we can test that this works, we'll set this + * to ALT_1 + */ + PERCFG = (PERCFG_U1CFG_ALT_1 | + PERCFG_U0CFG_ALT_2); + + /* + * Make the SPI pins controlled by the SPI + * hardware + */ + P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3)); + + /* + * SPI in master mode + */ + U0CSR = (UxCSR_MODE_SPI | + UxCSR_MASTER); + + /* + * The cc1111 is limited to a 24/8 MHz SPI clock, + * while the 25LC1024 is limited to 20MHz. So, + * use the 3MHz clock (BAUD_E 17, BAUD_M 0) + */ + U0BAUD = 0; + U0GCR = (UxGCR_CPOL_NEGATIVE | + UxGCR_CPHA_FIRST_EDGE | + UxGCR_ORDER_MSB | + (17 << UxGCR_BAUD_E_SHIFT)); +} + +void +usart_cs(uint8_t b) +{ + CS = b; +} + +uint8_t +usart_in_out(uint8_t byte) +{ + U0DBUF = byte; + while ((U0CSR & UxCSR_TX_BYTE) == 0) + ; +} + +void +usart_out_byte(uint8_t byte) +{ + (void) usart_in_out(byte); +} + +uint8_t +usart_in_byte(void) +{ + return usart_in_out(0xff); +} + +#define spi_init() usart_init() +#define spi_out_byte(b) usart_out_byte(b) +#define spi_in_byte() usart_in_byte() +#define spi_cs(b) usart_cs(b) + +#endif + uint8_t rdsr(void) { uint8_t status; - cs(0); - out_byte(0x05); - status = in_byte(); - cs(1); + spi_cs(0); + spi_out_byte(0x05); + status = spi_in_byte(); + spi_cs(1); return status; } void wrsr(uint8_t status) { - cs(0); - out_byte(0x01); - out_byte(status); - cs(1); + spi_cs(0); + spi_out_byte(0x01); + spi_out_byte(status); + spi_cs(1); } void wren(void) { - cs(0); - out_byte(0x06); - cs(1); + spi_cs(0); + spi_out_byte(0x06); + spi_cs(1); } void write(uint32_t addr, uint8_t *bytes, uint16_t len) { wren(); - cs(0); - out_byte(0x02); - out_byte(addr >> 16); - out_byte(addr >> 8); - out_byte(addr); + spi_cs(0); + spi_out_byte(0x02); + spi_out_byte(addr >> 16); + spi_out_byte(addr >> 8); + spi_out_byte(addr); while (len-- > 0) - out_byte(*bytes++); - cs(1); + spi_out_byte(*bytes++); + spi_cs(1); for (;;) { uint8_t status = rdsr(); if ((status & (1 << 0)) == 0) @@ -178,14 +344,14 @@ write(uint32_t addr, uint8_t *bytes, uint16_t len) void read(uint32_t addr, uint8_t *bytes, uint16_t len) { - cs(0); - out_byte(0x03); - out_byte(addr >> 16); - out_byte(addr >> 8); - out_byte(addr); + spi_cs(0); + spi_out_byte(0x03); + spi_out_byte(addr >> 16); + spi_out_byte(addr >> 8); + spi_out_byte(addr); while (len-- > 0) - *bytes++ = in_byte(); - cs(1); + *bytes++ = spi_in_byte(); + spi_cs(1); } void @@ -195,7 +361,7 @@ debug_byte(uint8_t byte) for (s = 0; s < 8; s++) { DEBUG = byte & 1; - delay(2); + delay(5); byte >>= 1; } } @@ -211,13 +377,8 @@ main () CLKCON = 0; - CS = 1; - SCK = 0; - P1DIR = ((1 << 5) | - (0 << 4) | - (1 << 3) | - (1 << 2) | - (1 << 1)); + spi_init(); + status = rdsr(); /* * Turn off both block-protect bits @@ -228,10 +389,10 @@ main () */ status &= ~(1 << 7); wrsr(status); - write(0x0, STRING, LENGTH); +// write(0x0, STRING, LENGTH); for (;;) { read(0x0, buf, LENGTH); for (i = 0; i < LENGTH; i++) - debug_byte(buf[i]); + debug_byte(STRING[i]); } } -- cgit v1.2.3 From 91b3a6ae74184692f45702587c4d678b2799ad8c Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 19:55:04 -0700 Subject: actually write and compare SPI test bits --- target/ee/ee.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target') diff --git a/target/ee/ee.c b/target/ee/ee.c index 68b6e4cc..d269d2aa 100644 --- a/target/ee/ee.c +++ b/target/ee/ee.c @@ -389,10 +389,10 @@ main () */ status &= ~(1 << 7); wrsr(status); -// write(0x0, STRING, LENGTH); + write(0x0, STRING, LENGTH); for (;;) { read(0x0, buf, LENGTH); for (i = 0; i < LENGTH; i++) - debug_byte(STRING[i]); + debug_byte(buf[i]); } } -- cgit v1.2.3 From 3ed3ff63e46767a256d30c5da5c52ae20089a91d Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 20:04:58 -0700 Subject: Led the LED turn on --- target/ee/ee.c | 1 + 1 file changed, 1 insertion(+) (limited to 'target') diff --git a/target/ee/ee.c b/target/ee/ee.c index d269d2aa..6cf276a0 100644 --- a/target/ee/ee.c +++ b/target/ee/ee.c @@ -375,6 +375,7 @@ main () uint8_t buf[LENGTH]; int i; + P1DIR |= 2; CLKCON = 0; spi_init(); -- cgit v1.2.3 From de1ac6f99a1526fa840a52cfc10fa3edc0589bed Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 22:12:51 -0700 Subject: Clear UxCSR_TX_BYTE after transmitting a byte --- target/ee/ee.c | 1 + 1 file changed, 1 insertion(+) (limited to 'target') diff --git a/target/ee/ee.c b/target/ee/ee.c index 6cf276a0..ed13d0ad 100644 --- a/target/ee/ee.c +++ b/target/ee/ee.c @@ -273,6 +273,7 @@ usart_in_out(uint8_t byte) U0DBUF = byte; while ((U0CSR & UxCSR_TX_BYTE) == 0) ; + U0CSR &= ~UxCSR_TX_BYTE; } void -- cgit v1.2.3 From e120269fc0f8e14ddf1755337b1d092173e16da2 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 22:21:31 -0700 Subject: Actually return byte read from SPI --- target/ee/ee.c | 1 + 1 file changed, 1 insertion(+) (limited to 'target') diff --git a/target/ee/ee.c b/target/ee/ee.c index ed13d0ad..08d55137 100644 --- a/target/ee/ee.c +++ b/target/ee/ee.c @@ -274,6 +274,7 @@ usart_in_out(uint8_t byte) while ((U0CSR & UxCSR_TX_BYTE) == 0) ; U0CSR &= ~UxCSR_TX_BYTE; + return U0DBUF; } void -- cgit v1.2.3 From 8ecbd8734f0fb5588b2a8eb20720cfc6f43dfb47 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 22:37:38 -0700 Subject: Wait for xtal to stabilize after changing to 24MHz --- target/ee/ee.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'target') diff --git a/target/ee/ee.c b/target/ee/ee.c index 08d55137..7cc47120 100644 --- a/target/ee/ee.c +++ b/target/ee/ee.c @@ -26,6 +26,10 @@ sfr at 0x80 P0; sfr at 0x90 P1; sfr at 0xA0 P2; sfr at 0xC6 CLKCON; +sfr at 0xbe SLEEP; + +# define SLEEP_USB_EN (1 << 7) +# define SLEEP_XOSC_STB (1 << 6) sfr at 0xF1 PERCFG; #define PERCFG_T1CFG_ALT_1 (0 << 6) @@ -379,6 +383,8 @@ main () P1DIR |= 2; CLKCON = 0; + while (!(SLEEP & SLEEP_XOSC_STB)) + ; spi_init(); -- cgit v1.2.3 From c35de083ca3d4f362063b056a0fd74ffe629d168 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 23:11:48 -0700 Subject: Add serial test program --- target/serial/Makefile | 46 +++++++++ target/serial/serial.c | 253 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 299 insertions(+) create mode 100644 target/serial/Makefile create mode 100644 target/serial/serial.c (limited to 'target') diff --git a/target/serial/Makefile b/target/serial/Makefile new file mode 100644 index 00000000..3a1d81e8 --- /dev/null +++ b/target/serial/Makefile @@ -0,0 +1,46 @@ +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse \ + --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large $(DEBUG) --less-pedantic \ + --no-peep --int-long-reent --float-reent \ + --data-loc 0x30 + +LDFLAGS=--out-fmt-ihx +LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf800 --xram-size 1024 + +LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 + +SRC=serial.c +ADB=$(SRC:.c=.adb) +ASM=$(SRC:.c=.asm) +LNK=$(SRC:.c=.lnk) +LST=$(SRC:.c=.lst) +REL=$(SRC:.c=.rel) +RST=$(SRC:.c=.rst) +SYM=$(SRC:.c=.sym) + +PROGS=serial-flash.ihx serial-ram.ihx +PCDB=$(PROGS:.ihx=.cdb) +PLNK=$(PROGS:.ihx=.lnk) +PMAP=$(PROGS:.ihx=.map) +PMEM=$(PROGS:.ihx=.mem) +PAOM=$(PROGS:.ihx=) + +%.rel : %.c + $(CC) -c $(CFLAGS) -o$*.rel $< + +all: $(PROGS) + +serial-ram.ihx: $(REL) Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o serial-ram.ihx $(REL) + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o serial-flash.ihx $(REL) + +serial-flash.ihx: serial-ram.ihx + +clean: + rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) + rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) + +install: diff --git a/target/serial/serial.c b/target/serial/serial.c new file mode 100644 index 00000000..5acd284f --- /dev/null +++ b/target/serial/serial.c @@ -0,0 +1,253 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include + +/* + * Validate UART1 + */ + +sfr at 0x80 P0; +sfr at 0x90 P1; +sfr at 0xA0 P2; +sfr at 0xC6 CLKCON; +sfr at 0xbe SLEEP; + +# define SLEEP_USB_EN (1 << 7) +# define SLEEP_XOSC_STB (1 << 6) + +sfr at 0xF1 PERCFG; +#define PERCFG_T1CFG_ALT_1 (0 << 6) +#define PERCFG_T1CFG_ALT_2 (1 << 6) + +#define PERCFG_T3CFG_ALT_1 (0 << 5) +#define PERCFG_T3CFG_ALT_2 (1 << 5) + +#define PERCFG_T4CFG_ALT_1 (0 << 4) +#define PERCFG_T4CFG_ALT_2 (1 << 4) + +#define PERCFG_U1CFG_ALT_1 (0 << 1) +#define PERCFG_U1CFG_ALT_2 (1 << 1) + +#define PERCFG_U0CFG_ALT_1 (0 << 0) +#define PERCFG_U0CFG_ALT_2 (1 << 0) + +sfr at 0xF2 ADCCFG; +sfr at 0xF3 P0SEL; +sfr at 0xF4 P1SEL; +sfr at 0xF5 P2SEL; + +sfr at 0xFD P0DIR; +sfr at 0xFE P1DIR; +sfr at 0xFF P2DIR; +sfr at 0x8F P0INP; +sfr at 0xF6 P1INP; +sfr at 0xF7 P2INP; + +sfr at 0x89 P0IFG; +sfr at 0x8A P1IFG; +sfr at 0x8B P2IFG; + +sbit at 0x90 P1_0; +sbit at 0x91 P1_1; +sbit at 0x92 P1_2; +sbit at 0x93 P1_3; +sbit at 0x94 P1_4; +sbit at 0x95 P1_5; +sbit at 0x96 P1_6; +sbit at 0x97 P1_7; + +/* + * UART registers + */ + +sfr at 0x86 U0CSR; +sfr at 0xF8 U1CSR; + +# define UxCSR_MODE_UART (1 << 7) +# define UxCSR_MODE_SPI (0 << 7) +# define UxCSR_RE (1 << 6) +# define UxCSR_SLAVE (1 << 5) +# define UxCSR_MASTER (0 << 5) +# define UxCSR_FE (1 << 4) +# define UxCSR_ERR (1 << 3) +# define UxCSR_RX_BYTE (1 << 2) +# define UxCSR_TX_BYTE (1 << 1) +# define UxCSR_ACTIVE (1 << 0) + +sfr at 0xc4 U0UCR; +sfr at 0xfb U1UCR; + +# define UxUCR_FLUSH (1 << 7) +# define UxUCR_FLOW_DISABLE (0 << 6) +# define UxUCR_FLOW_ENABLE (1 << 6) +# define UxUCR_D9_EVEN_PARITY (0 << 5) +# define UxUCR_D9_ODD_PARITY (1 << 5) +# define UxUCR_BIT9_8_BITS (0 << 4) +# define UxUCR_BIT9_9_BITS (1 << 4) +# define UxUCR_PARITY_DISABLE (0 << 3) +# define UxUCR_PARITY_ENABLE (1 << 3) +# define UxUCR_SPB_1_STOP_BIT (0 << 2) +# define UxUCR_SPB_2_STOP_BITS (1 << 2) +# define UxUCR_STOP_LOW (0 << 1) +# define UXUCR_STOP_HIGH (1 << 1) +# define UxUCR_START_LOW (0 << 0) +# define UxUCR_START_HIGH (1 << 0) + +sfr at 0xc5 U0GCR; +sfr at 0xfc U1GCR; + +# define UxGCR_CPOL_NEGATIVE (0 << 7) +# define UxGCR_CPOL_POSITIVE (1 << 7) +# define UxGCR_CPHA_FIRST_EDGE (0 << 6) +# define UxGCR_CPHA_SECOND_EDGE (1 << 6) +# define UxGCR_ORDER_LSB (0 << 5) +# define UxGCR_ORDER_MSB (1 << 5) +# define UxGCR_BAUD_E_MASK (0x1f) +# define UxGCR_BAUD_E_SHIFT 0 + +sfr at 0xc1 U0DBUF; +sfr at 0xf9 U1DBUF; +sfr at 0xc2 U0BAUD; +sfr at 0xfa U1BAUD; + +#define MOSI P1_5 +#define MISO P1_4 +#define SCK P1_3 +#define CS P1_2 + +#define DEBUG P1_1 + +#define USART 1 + +#define nop() _asm nop _endasm; + +void +delay (unsigned char n) +{ + unsigned char i = 0; + unsigned char j = 0; + + while (--n != 0) + while (--i != 0) + while (--j != 0) + nop(); +} + +/* + * This version uses the USART in SPI mode + */ +void +usart_init(void) +{ + P1DIR |= (1 << 2); + /* + * Configure the peripheral pin choices + * for both of the serial ports + * + * Note that telemetrum will use U1CFG_ALT_2 + * but that overlaps with SPI ALT_2, so until + * we can test that this works, we'll set this + * to ALT_1 + */ + PERCFG = (PERCFG_U1CFG_ALT_2 | + PERCFG_U0CFG_ALT_1); + + /* + * Make the UART pins controlled by the UART + * hardware + */ + P1SEL |= ((1 << 6) | (1 << 7)); + + /* + * UART mode with the receiver enabled + */ + U1CSR = (UxCSR_MODE_UART | + UxCSR_RE); + /* + * Pick a 38.4kbaud rate + */ + U1BAUD = 163; + U1GCR = 10 << UxGCR_BAUD_E_SHIFT; /* 38400 */ +// U1GCR = 3 << UxGCR_BAUD_E_SHIFT; /* 300 */ + /* + * Reasonable serial parameters + */ + U1UCR = (UxUCR_FLOW_DISABLE | + UxUCR_D9_EVEN_PARITY | + UxUCR_BIT9_8_BITS | + UxUCR_PARITY_DISABLE | + UxUCR_SPB_1_STOP_BIT | + UxUCR_STOP_LOW | + UxUCR_START_LOW); +} + + +uint8_t +usart_in_out(uint8_t byte) +{ + U1DBUF = byte; + while ((U1CSR & UxCSR_TX_BYTE) == 0) + ; + U1CSR &= ~UxCSR_TX_BYTE; + return U1DBUF; +} +void +usart_out_byte(uint8_t byte) +{ + U1CSR &= ~UxCSR_TX_BYTE; + U1DBUF = byte; + while ((U1CSR & UxCSR_TX_BYTE) == 0) + ; +} + +uint8_t +usart_in_byte(void) +{ + uint8_t b; + while ((U1CSR & UxCSR_RX_BYTE) == 0) + ; + b = U1DBUF; + U1CSR &= ~UxCSR_RX_BYTE; + return b; +} + +#define spi_init() usart_init() +#define spi_out_byte(b) usart_out_byte(b) +#define spi_in_byte() usart_in_byte() + +static char string[] = "hello world\r\n"; + +main () +{ + uint8_t i; + + P1DIR |= 2; + CLKCON = 0; + while (!(SLEEP & SLEEP_XOSC_STB)) + ; + + spi_init(); + + for (;;) { + for (i = 0; i < sizeof (string) - 1; i++) { + usart_out_byte(string[i]); + } + P1 ^= 2; + } +} -- cgit v1.2.3 From c41ceb9a488b2209d1d3c09967d1473ce608030f Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 23:24:01 -0700 Subject: Change radio to -30dBm --- target/radio/radio.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) (limited to 'target') diff --git a/target/radio/radio.c b/target/radio/radio.c index 9f10fccd..ba693a77 100644 --- a/target/radio/radio.c +++ b/target/radio/radio.c @@ -416,15 +416,29 @@ low() { #define PACKET_LEN 128 +/* This are from the table for 433MHz */ + +#define RF_POWER_M30_DBM 0x12 +#define RF_POWER_M20_DBM 0x0e +#define RF_POWER_M15_DBM 0x1d +#define RF_POWER_M10_DBM 0x34 +#define RF_POWER_M5_DBM 0x2c +#define RF_POWER_0_DBM 0x60 +#define RF_POWER_5_DBM 0x84 +#define RF_POWER_7_DBM 0xc8 +#define RF_POWER_10_DBM 0xc0 + +#define RF_POWER RF_POWER_M30_DBM + static __code uint8_t radio_setup[] = { - RF_PA_TABLE7_OFF, 0x60, - RF_PA_TABLE6_OFF, 0x60, - RF_PA_TABLE5_OFF, 0x60, - RF_PA_TABLE4_OFF, 0x60, - RF_PA_TABLE3_OFF, 0x60, - RF_PA_TABLE2_OFF, 0x60, - RF_PA_TABLE1_OFF, 0x60, - RF_PA_TABLE0_OFF, 0x60, + RF_PA_TABLE7_OFF, RF_POWER, + RF_PA_TABLE6_OFF, RF_POWER, + RF_PA_TABLE5_OFF, RF_POWER, + RF_PA_TABLE4_OFF, RF_POWER, + RF_PA_TABLE3_OFF, RF_POWER, + RF_PA_TABLE2_OFF, RF_POWER, + RF_PA_TABLE1_OFF, RF_POWER, + RF_PA_TABLE0_OFF, RF_POWER, RF_FREQ2_OFF, FREQ_CONTROL >> 16, RF_FREQ1_OFF, FREQ_CONTROL >> 8, -- cgit v1.2.3 From 9e96107d5d1a9681b07c36bb5860c748bfe10ec0 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 24 Mar 2009 23:57:12 -0700 Subject: Stop high --- target/serial/serial.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) (limited to 'target') diff --git a/target/serial/serial.c b/target/serial/serial.c index 5acd284f..b0aead74 100644 --- a/target/serial/serial.c +++ b/target/serial/serial.c @@ -105,7 +105,7 @@ sfr at 0xfb U1UCR; # define UxUCR_SPB_1_STOP_BIT (0 << 2) # define UxUCR_SPB_2_STOP_BITS (1 << 2) # define UxUCR_STOP_LOW (0 << 1) -# define UXUCR_STOP_HIGH (1 << 1) +# define UxUCR_STOP_HIGH (1 << 1) # define UxUCR_START_LOW (0 << 0) # define UxUCR_START_HIGH (1 << 0) @@ -193,20 +193,10 @@ usart_init(void) UxUCR_BIT9_8_BITS | UxUCR_PARITY_DISABLE | UxUCR_SPB_1_STOP_BIT | - UxUCR_STOP_LOW | + UxUCR_STOP_HIGH | UxUCR_START_LOW); } - -uint8_t -usart_in_out(uint8_t byte) -{ - U1DBUF = byte; - while ((U1CSR & UxCSR_TX_BYTE) == 0) - ; - U1CSR &= ~UxCSR_TX_BYTE; - return U1DBUF; -} void usart_out_byte(uint8_t byte) { -- cgit v1.2.3 From 62744c186792739c3bf5798c80ff87c69fbe2b65 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 00:03:45 -0700 Subject: Flip start/stop bits around --- target/serial/serial.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target') diff --git a/target/serial/serial.c b/target/serial/serial.c index b0aead74..6065d971 100644 --- a/target/serial/serial.c +++ b/target/serial/serial.c @@ -193,8 +193,8 @@ usart_init(void) UxUCR_BIT9_8_BITS | UxUCR_PARITY_DISABLE | UxUCR_SPB_1_STOP_BIT | - UxUCR_STOP_HIGH | - UxUCR_START_LOW); + UxUCR_STOP_LOW | + UxUCR_START_HIGH); } void -- cgit v1.2.3 From 18edacdb1e6e429cc29a164e22ef2a566096b9d9 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 00:06:32 -0700 Subject: Make serial test simpler --- target/serial/serial.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'target') diff --git a/target/serial/serial.c b/target/serial/serial.c index 6065d971..6db81ae9 100644 --- a/target/serial/serial.c +++ b/target/serial/serial.c @@ -235,9 +235,8 @@ main () spi_init(); for (;;) { - for (i = 0; i < sizeof (string) - 1; i++) { - usart_out_byte(string[i]); - } + usart_out_byte('A'); + delay(5); P1 ^= 2; } } -- cgit v1.2.3 From 7b7617e376afe0df1d505375b76198358330370c Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 00:09:47 -0700 Subject: Try serial polarity high/high --- target/serial/serial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/serial/serial.c b/target/serial/serial.c index 6db81ae9..ecf065a2 100644 --- a/target/serial/serial.c +++ b/target/serial/serial.c @@ -193,7 +193,7 @@ usart_init(void) UxUCR_BIT9_8_BITS | UxUCR_PARITY_DISABLE | UxUCR_SPB_1_STOP_BIT | - UxUCR_STOP_LOW | + UxUCR_STOP_HIGH | UxUCR_START_HIGH); } -- cgit v1.2.3 From 50bdc2407c674a4770912d3a626f36820a7f1527 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 00:13:15 -0700 Subject: Flip serial TX code around a bit --- target/serial/serial.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target') diff --git a/target/serial/serial.c b/target/serial/serial.c index ecf065a2..d2be47fd 100644 --- a/target/serial/serial.c +++ b/target/serial/serial.c @@ -194,16 +194,16 @@ usart_init(void) UxUCR_PARITY_DISABLE | UxUCR_SPB_1_STOP_BIT | UxUCR_STOP_HIGH | - UxUCR_START_HIGH); + UxUCR_START_LOW); } void usart_out_byte(uint8_t byte) { - U1CSR &= ~UxCSR_TX_BYTE; U1DBUF = byte; while ((U1CSR & UxCSR_TX_BYTE) == 0) ; + U1CSR &= ~UxCSR_TX_BYTE; } uint8_t -- cgit v1.2.3 From 5049acd3d1ae42304513f667f55a2ddffa4c685a Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 00:24:56 -0700 Subject: More random serial bit frobbing --- target/serial/serial.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'target') diff --git a/target/serial/serial.c b/target/serial/serial.c index d2be47fd..589452c0 100644 --- a/target/serial/serial.c +++ b/target/serial/serial.c @@ -188,11 +188,12 @@ usart_init(void) /* * Reasonable serial parameters */ - U1UCR = (UxUCR_FLOW_DISABLE | - UxUCR_D9_EVEN_PARITY | + U1UCR = (UxUCR_FLUSH | + UxUCR_FLOW_DISABLE | + UxUCR_D9_ODD_PARITY | UxUCR_BIT9_8_BITS | UxUCR_PARITY_DISABLE | - UxUCR_SPB_1_STOP_BIT | + UxUCR_SPB_2_STOP_BITS | UxUCR_STOP_HIGH | UxUCR_START_LOW); } -- cgit v1.2.3 From 006124529b243c7657a94312d2c868a82878d8bb Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 00:29:29 -0700 Subject: Send more interesting text --- target/serial/serial.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'target') diff --git a/target/serial/serial.c b/target/serial/serial.c index 589452c0..42705d71 100644 --- a/target/serial/serial.c +++ b/target/serial/serial.c @@ -236,7 +236,8 @@ main () spi_init(); for (;;) { - usart_out_byte('A'); + for (i = 0; i < sizeof(string) - 1; i++) + usart_out_byte(string[i]); delay(5); P1 ^= 2; } -- cgit v1.2.3 From cfaf187e96ba98eb8dd934409a10bc70273fe68a Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 00:36:35 -0700 Subject: Use UTX1IF to wait for serial TX complete --- target/serial/serial.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'target') diff --git a/target/serial/serial.c b/target/serial/serial.c index 42705d71..1050b9a6 100644 --- a/target/serial/serial.c +++ b/target/serial/serial.c @@ -79,6 +79,19 @@ sbit at 0x97 P1_7; sfr at 0x86 U0CSR; sfr at 0xF8 U1CSR; +/* + * IRCON2 + */ +sfr at 0xE8 IRCON2; /* CPU Interrupt Flag 5 */ + +sbit at 0xE8 USBIF; /* USB interrupt flag (shared with Port2) */ +sbit at 0xE8 P2IF; /* Port2 interrupt flag (shared with USB) */ +sbit at 0xE9 UTX0IF; /* USART0 TX interrupt flag */ +sbit at 0xEA UTX1IF; /* USART1 TX interrupt flag (shared with I2S TX) */ +sbit at 0xEA I2STXIF; /* I2S TX interrupt flag (shared with USART1 TX) */ +sbit at 0xEB P1IF; /* Port1 interrupt flag */ +sbit at 0xEC WDTIF; /* Watchdog timer interrupt flag */ + # define UxCSR_MODE_UART (1 << 7) # define UxCSR_MODE_SPI (0 << 7) # define UxCSR_RE (1 << 6) @@ -193,7 +206,7 @@ usart_init(void) UxUCR_D9_ODD_PARITY | UxUCR_BIT9_8_BITS | UxUCR_PARITY_DISABLE | - UxUCR_SPB_2_STOP_BITS | + UxUCR_SPB_1_STOP_BIT | UxUCR_STOP_HIGH | UxUCR_START_LOW); } @@ -202,9 +215,8 @@ void usart_out_byte(uint8_t byte) { U1DBUF = byte; - while ((U1CSR & UxCSR_TX_BYTE) == 0) - ; - U1CSR &= ~UxCSR_TX_BYTE; + while (!UTX1IF); + UTX1IF = 0; } uint8_t -- cgit v1.2.3 From 019456a17d36f8f9f9b72cfbc980492175086d32 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 00:41:49 -0700 Subject: Add a per-char delay --- target/serial/serial.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'target') diff --git a/target/serial/serial.c b/target/serial/serial.c index 1050b9a6..1c352831 100644 --- a/target/serial/serial.c +++ b/target/serial/serial.c @@ -156,6 +156,7 @@ delay (unsigned char n) unsigned char i = 0; unsigned char j = 0; + n++; while (--n != 0) while (--i != 0) while (--j != 0) @@ -215,8 +216,10 @@ void usart_out_byte(uint8_t byte) { U1DBUF = byte; - while (!UTX1IF); + while (!UTX1IF) + ; UTX1IF = 0; + delay(1); } uint8_t @@ -230,10 +233,6 @@ usart_in_byte(void) return b; } -#define spi_init() usart_init() -#define spi_out_byte(b) usart_out_byte(b) -#define spi_in_byte() usart_in_byte() - static char string[] = "hello world\r\n"; main () @@ -245,7 +244,7 @@ main () while (!(SLEEP & SLEEP_XOSC_STB)) ; - spi_init(); + usart_init(); for (;;) { for (i = 0; i < sizeof(string) - 1; i++) -- cgit v1.2.3 From 029963cc94fbb47560118b5de73c537e2c14ed7c Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 00:50:02 -0700 Subject: Eliminate array walking --- target/serial/serial.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'target') diff --git a/target/serial/serial.c b/target/serial/serial.c index 1c352831..ebe7e2fc 100644 --- a/target/serial/serial.c +++ b/target/serial/serial.c @@ -207,7 +207,7 @@ usart_init(void) UxUCR_D9_ODD_PARITY | UxUCR_BIT9_8_BITS | UxUCR_PARITY_DISABLE | - UxUCR_SPB_1_STOP_BIT | + UxUCR_SPB_2_STOP_BITS | UxUCR_STOP_HIGH | UxUCR_START_LOW); } @@ -219,7 +219,15 @@ usart_out_byte(uint8_t byte) while (!UTX1IF) ; UTX1IF = 0; - delay(1); +} + +void +usart_out_string(uint8_t *string) +{ + uint8_t b; + + while (b = *string++) + usart_out_byte(b); } uint8_t @@ -233,12 +241,8 @@ usart_in_byte(void) return b; } -static char string[] = "hello world\r\n"; - main () { - uint8_t i; - P1DIR |= 2; CLKCON = 0; while (!(SLEEP & SLEEP_XOSC_STB)) @@ -247,8 +251,7 @@ main () usart_init(); for (;;) { - for (i = 0; i < sizeof(string) - 1; i++) - usart_out_byte(string[i]); + usart_out_string("hello world\r\n"); delay(5); P1 ^= 2; } -- cgit v1.2.3 From ffd43886dc902f3bb7407294018e3d62cac39480 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 00:55:11 -0700 Subject: Check serial input --- target/serial/serial.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'target') diff --git a/target/serial/serial.c b/target/serial/serial.c index ebe7e2fc..29390426 100644 --- a/target/serial/serial.c +++ b/target/serial/serial.c @@ -241,6 +241,18 @@ usart_in_byte(void) return b; } +void +debug_byte(uint8_t byte) +{ + uint8_t s; + + for (s = 0; s < 8; s++) { + DEBUG = byte & 1; + delay(5); + byte >>= 1; + } +} + main () { P1DIR |= 2; @@ -252,7 +264,7 @@ main () for (;;) { usart_out_string("hello world\r\n"); - delay(5); - P1 ^= 2; + debug_byte(usart_in_byte()); } + } -- cgit v1.2.3 From 9ce713fdd19bf1a51370dacba3670504356c5c11 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 01:02:07 -0700 Subject: Wait for xtal to stabilize --- target/radio/radio.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'target') diff --git a/target/radio/radio.c b/target/radio/radio.c index ba693a77..d6c49eff 100644 --- a/target/radio/radio.c +++ b/target/radio/radio.c @@ -518,6 +518,8 @@ radio_init() { main () { CLKCON = 0; + while (!(SLEEP & SLEEP_XOSC_STB)) + ; /* Set P2_0 to output */ radio_init (); delay(100); -- cgit v1.2.3 From 31d59b88baa2cd96dc6263d1c5877283f2cd8c36 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 01:03:08 -0700 Subject: Make radio test compile again --- target/radio/radio.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'target') diff --git a/target/radio/radio.c b/target/radio/radio.c index d6c49eff..3ca7a010 100644 --- a/target/radio/radio.c +++ b/target/radio/radio.c @@ -46,6 +46,11 @@ sfr at 0xE1 RFST; sfr at 0x88 TCON; +sfr at 0xbe SLEEP; + +# define SLEEP_USB_EN (1 << 7) +# define SLEEP_XOSC_STB (1 << 6) + sbit at 0x89 RFTXRXIF; #define TCON_RFTXRXIF (1 << 1) -- cgit v1.2.3 From 7b3fdf5b42c9be9bebc1ceb7a52ff0f5a2a28fcd Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 01:05:36 -0700 Subject: Back to 0dBm --- target/radio/radio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/radio/radio.c b/target/radio/radio.c index 3ca7a010..90bc47f3 100644 --- a/target/radio/radio.c +++ b/target/radio/radio.c @@ -433,7 +433,7 @@ low() { #define RF_POWER_7_DBM 0xc8 #define RF_POWER_10_DBM 0xc0 -#define RF_POWER RF_POWER_M30_DBM +#define RF_POWER RF_POWER_0_DBM static __code uint8_t radio_setup[] = { RF_PA_TABLE7_OFF, RF_POWER, -- cgit v1.2.3 From 61faf2b773300988fe27cfde5bc045be9950a1b0 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 09:45:14 -0700 Subject: Add DMA example --- target/dma/Makefile | 46 +++++++ target/dma/dma.c | 361 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 407 insertions(+) create mode 100644 target/dma/Makefile create mode 100644 target/dma/dma.c (limited to 'target') diff --git a/target/dma/Makefile b/target/dma/Makefile new file mode 100644 index 00000000..9cb3e327 --- /dev/null +++ b/target/dma/Makefile @@ -0,0 +1,46 @@ +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse \ + --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large $(DEBUG) --less-pedantic \ + --no-peep --int-long-reent --float-reent \ + --data-loc 0x30 + +LDFLAGS=--out-fmt-ihx +LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf800 --xram-size 1024 + +LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 + +SRC=dma.c +ADB=$(SRC:.c=.adb) +ASM=$(SRC:.c=.asm) +LNK=$(SRC:.c=.lnk) +LST=$(SRC:.c=.lst) +REL=$(SRC:.c=.rel) +RST=$(SRC:.c=.rst) +SYM=$(SRC:.c=.sym) + +PROGS=dma-flash.ihx dma-ram.ihx +PCDB=$(PROGS:.ihx=.cdb) +PLNK=$(PROGS:.ihx=.lnk) +PMAP=$(PROGS:.ihx=.map) +PMEM=$(PROGS:.ihx=.mem) +PAOM=$(PROGS:.ihx=) + +%.rel : %.c + $(CC) -c $(CFLAGS) -o$*.rel $< + +all: $(PROGS) + +dma-ram.ihx: $(REL) Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o dma-ram.ihx $(REL) + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o dma-flash.ihx $(REL) + +dma-flash.ihx: dma-ram.ihx + +clean: + rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) + rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) + +install: diff --git a/target/dma/dma.c b/target/dma/dma.c new file mode 100644 index 00000000..c35c39f6 --- /dev/null +++ b/target/dma/dma.c @@ -0,0 +1,361 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include + +/* + * Test DMA + */ + +sfr at 0x80 P0; +sfr at 0x90 P1; +sfr at 0xA0 P2; +sfr at 0xC6 CLKCON; +sfr at 0xbe SLEEP; + +# define SLEEP_USB_EN (1 << 7) +# define SLEEP_XOSC_STB (1 << 6) + +sfr at 0xF1 PERCFG; +#define PERCFG_T1CFG_ALT_1 (0 << 6) +#define PERCFG_T1CFG_ALT_2 (1 << 6) + +#define PERCFG_T3CFG_ALT_1 (0 << 5) +#define PERCFG_T3CFG_ALT_2 (1 << 5) + +#define PERCFG_T4CFG_ALT_1 (0 << 4) +#define PERCFG_T4CFG_ALT_2 (1 << 4) + +#define PERCFG_U1CFG_ALT_1 (0 << 1) +#define PERCFG_U1CFG_ALT_2 (1 << 1) + +#define PERCFG_U0CFG_ALT_1 (0 << 0) +#define PERCFG_U0CFG_ALT_2 (1 << 0) + +sfr at 0xF2 ADCCFG; +sfr at 0xF3 P0SEL; +sfr at 0xF4 P1SEL; +sfr at 0xF5 P2SEL; + +sfr at 0xFD P0DIR; +sfr at 0xFE P1DIR; +sfr at 0xFF P2DIR; +sfr at 0x8F P0INP; +sfr at 0xF6 P1INP; +sfr at 0xF7 P2INP; + +sfr at 0x89 P0IFG; +sfr at 0x8A P1IFG; +sfr at 0x8B P2IFG; + +sbit at 0x90 P1_0; +sbit at 0x91 P1_1; +sbit at 0x92 P1_2; +sbit at 0x93 P1_3; +sbit at 0x94 P1_4; +sbit at 0x95 P1_5; +sbit at 0x96 P1_6; +sbit at 0x97 P1_7; + +/* + * UART registers + */ + +sfr at 0x86 U0CSR; +sfr at 0xF8 U1CSR; + +/* + * IRCON2 + */ +sfr at 0xE8 IRCON2; /* CPU Interrupt Flag 5 */ + +sbit at 0xE8 USBIF; /* USB interrupt flag (shared with Port2) */ +sbit at 0xE8 P2IF; /* Port2 interrupt flag (shared with USB) */ +sbit at 0xE9 UTX0IF; /* USART0 TX interrupt flag */ +sbit at 0xEA UTX1IF; /* USART1 TX interrupt flag (shared with I2S TX) */ +sbit at 0xEA I2STXIF; /* I2S TX interrupt flag (shared with USART1 TX) */ +sbit at 0xEB P1IF; /* Port1 interrupt flag */ +sbit at 0xEC WDTIF; /* Watchdog timer interrupt flag */ + +# define UxCSR_MODE_UART (1 << 7) +# define UxCSR_MODE_SPI (0 << 7) +# define UxCSR_RE (1 << 6) +# define UxCSR_SLAVE (1 << 5) +# define UxCSR_MASTER (0 << 5) +# define UxCSR_FE (1 << 4) +# define UxCSR_ERR (1 << 3) +# define UxCSR_RX_BYTE (1 << 2) +# define UxCSR_TX_BYTE (1 << 1) +# define UxCSR_ACTIVE (1 << 0) + +sfr at 0xc4 U0UCR; +sfr at 0xfb U1UCR; + +# define UxUCR_FLUSH (1 << 7) +# define UxUCR_FLOW_DISABLE (0 << 6) +# define UxUCR_FLOW_ENABLE (1 << 6) +# define UxUCR_D9_EVEN_PARITY (0 << 5) +# define UxUCR_D9_ODD_PARITY (1 << 5) +# define UxUCR_BIT9_8_BITS (0 << 4) +# define UxUCR_BIT9_9_BITS (1 << 4) +# define UxUCR_PARITY_DISABLE (0 << 3) +# define UxUCR_PARITY_ENABLE (1 << 3) +# define UxUCR_SPB_1_STOP_BIT (0 << 2) +# define UxUCR_SPB_2_STOP_BITS (1 << 2) +# define UxUCR_STOP_LOW (0 << 1) +# define UxUCR_STOP_HIGH (1 << 1) +# define UxUCR_START_LOW (0 << 0) +# define UxUCR_START_HIGH (1 << 0) + +sfr at 0xc5 U0GCR; +sfr at 0xfc U1GCR; + +# define UxGCR_CPOL_NEGATIVE (0 << 7) +# define UxGCR_CPOL_POSITIVE (1 << 7) +# define UxGCR_CPHA_FIRST_EDGE (0 << 6) +# define UxGCR_CPHA_SECOND_EDGE (1 << 6) +# define UxGCR_ORDER_LSB (0 << 5) +# define UxGCR_ORDER_MSB (1 << 5) +# define UxGCR_BAUD_E_MASK (0x1f) +# define UxGCR_BAUD_E_SHIFT 0 + +sfr at 0xc1 U0DBUF; +sfr at 0xf9 U1DBUF; +sfr at 0xc2 U0BAUD; +sfr at 0xfa U1BAUD; + +#define DEBUG P1_1 + + +# define DMA_LEN_HIGH_VLEN_MASK (7 << 5) +# define DMA_LEN_HIGH_VLEN_LEN (0 << 5) +# define DMA_LEN_HIGH_VLEN_PLUS_1 (1 << 5) +# define DMA_LEN_HIGH_VLEN (2 << 5) +# define DMA_LEN_HIGH_VLEN_PLUS_2 (3 << 5) +# define DMA_LEN_HIGH_VLEN_PLUS_3 (4 << 5) +# define DMA_LEN_HIGH_MASK (0x1f) + +# define DMA_CFG0_WORDSIZE_8 (0 << 7) +# define DMA_CFG0_WORDSIZE_16 (1 << 7) +# define DMA_CFG0_TMODE_MASK (3 << 5) +# define DMA_CFG0_TMODE_SINGLE (0 << 5) +# define DMA_CFG0_TMODE_BLOCK (1 << 5) +# define DMA_CFG0_TMODE_REPEATED_SINGLE (2 << 5) +# define DMA_CFG0_TMODE_REPEATED_BLOCK (3 << 5) + +/* + * DMA triggers + */ +# define DMA_CFG0_TRIGGER_NONE 0 +# define DMA_CFG0_TRIGGER_PREV 1 +# define DMA_CFG0_TRIGGER_T1_CH0 2 +# define DMA_CFG0_TRIGGER_T1_CH1 3 +# define DMA_CFG0_TRIGGER_T1_CH2 4 +# define DMA_CFG0_TRIGGER_T2_OVFL 6 +# define DMA_CFG0_TRIGGER_T3_CH0 7 +# define DMA_CFG0_TRIGGER_T3_CH1 8 +# define DMA_CFG0_TRIGGER_T4_CH0 9 +# define DMA_CFG0_TRIGGER_T4_CH1 10 +# define DMA_CFG0_TRIGGER_IOC_0 12 +# define DMA_CFG0_TRIGGER_IOC_1 13 +# define DMA_CFG0_TRIGGER_URX0 14 +# define DMA_CFG0_TRIGGER_UTX0 15 +# define DMA_CFG0_TRIGGER_URX1 16 +# define DMA_CFG0_TRIGGER_UTX1 17 +# define DMA_CFG0_TRIGGER_FLASH 18 +# define DMA_CFG0_TRIGGER_RADIO 19 +# define DMA_CFG0_TRIGGER_ADC_CHALL 20 +# define DMA_CFG0_TRIGGER_ADC_CH0 21 +# define DMA_CFG0_TRIGGER_ADC_CH1 22 +# define DMA_CFG0_TRIGGER_ADC_CH2 23 +# define DMA_CFG0_TRIGGER_ADC_CH3 24 +# define DMA_CFG0_TRIGGER_ADC_CH4 25 +# define DMA_CFG0_TRIGGER_ADC_CH5 26 +# define DMA_CFG0_TRIGGER_ADC_CH6 27 +# define DMA_CFG0_TRIGGER_I2SRX 27 +# define DMA_CFG0_TRIGGER_ADC_CH7 28 +# define DMA_CFG0_TRIGGER_I2STX 28 +# define DMA_CFG0_TRIGGER_ENC_DW 29 +# define DMA_CFG0_TRIGGER_DNC_UP 30 + +# define DMA_CFG1_SRCINC_MASK (3 << 6) +# define DMA_CFG1_SRCINC_0 (0 << 6) +# define DMA_CFG1_SRCINC_1 (1 << 6) +# define DMA_CFG1_SRCINC_2 (2 << 6) +# define DMA_CFG1_SRCINC_MINUS_1 (3 << 6) + +# define DMA_CFG1_DESTINC_MASK (3 << 4) +# define DMA_CFG1_DESTINC_0 (0 << 4) +# define DMA_CFG1_DESTINC_1 (1 << 4) +# define DMA_CFG1_DESTINC_2 (2 << 4) +# define DMA_CFG1_DESTINC_MINUS_1 (3 << 4) + +# define DMA_CFG1_IRQMASK (1 << 3) +# define DMA_CFG1_M8 (1 << 2) + +# define DMA_CFG1_PRIORITY_MASK (3 << 0) +# define DMA_CFG1_PRIORITY_LOW (0 << 0) +# define DMA_CFG1_PRIORITY_NORMAL (1 << 0) +# define DMA_CFG1_PRIORITY_HIGH (2 << 0) + +/* + * DMAARM - DMA Channel Arm + */ + +sfr at 0xD6 DMAARM; + +# define DMAARM_ABORT (1 << 7) +# define DMAARM_DMAARM4 (1 << 4) +# define DMAARM_DMAARM3 (1 << 3) +# define DMAARM_DMAARM2 (1 << 2) +# define DMAARM_DMAARM1 (1 << 1) +# define DMAARM_DMAARM0 (1 << 0) + +/* + * DMAREQ - DMA Channel Start Request and Status + */ + +sfr at 0xD7 DMAREQ; + +# define DMAREQ_DMAREQ4 (1 << 4) +# define DMAREQ_DMAREQ3 (1 << 3) +# define DMAREQ_DMAREQ2 (1 << 2) +# define DMAREQ_DMAREQ1 (1 << 1) +# define DMAREQ_DMAREQ0 (1 << 0) + +/* + * DMA configuration 0 address + */ + +sfr at 0xD5 DMA0CFGH; +sfr at 0xD4 DMA0CFGL; + +/* + * DMA configuration 1-4 address + */ + +sfr at 0xD3 DMA1CFGH; +sfr at 0xD2 DMA1CFGL; + +/* + * DMAIRQ - DMA Interrupt Flag + */ + +sfr at 0xD1 DMAIRQ; + +# define DMAIRQ_DMAIF4 (1 << 4) +# define DMAIRQ_DMAIF3 (1 << 3) +# define DMAIRQ_DMAIF2 (1 << 2) +# define DMAIRQ_DMAIF1 (1 << 1) +# define DMAIRQ_DMAIF0 (1 << 0) + +struct cc_dma_channel { + uint8_t src_high; + uint8_t src_low; + uint8_t dst_high; + uint8_t dst_low; + uint8_t len_high; + uint8_t len_low; + uint8_t cfg0; + uint8_t cfg1; +}; + +#define nop() _asm nop _endasm; + +void +delay (unsigned char n) +{ + unsigned char i = 0; + unsigned char j = 0; + + n++; + while (--n != 0) + while (--i != 0) + while (--j != 0) + nop(); +} + +void +debug_byte(uint8_t byte) +{ + uint8_t s; + + for (s = 0; s < 8; s++) { + DEBUG = byte & 1; + delay(5); + byte >>= 1; + } +} + +struct cc_dma_channel __xdata config; + +#define DMA_LEN 8 + +uint8_t __xdata dma_input[DMA_LEN]; +uint8_t __xdata dma_output[DMA_LEN]; + +#define ADDRH(a) (((uint16_t) (a)) >> 8) +#define ADDRL(a) (((uint16_t) (a))) + +void +dma_init(void) +{ + int i; + config.cfg0 = (DMA_CFG0_WORDSIZE_8 | + DMA_CFG0_TMODE_BLOCK | + DMA_CFG0_TRIGGER_NONE); + config.cfg1 = (DMA_CFG1_SRCINC_1 | + DMA_CFG1_DESTINC_1 | + DMA_CFG1_PRIORITY_NORMAL); + + config.src_high = ADDRH(dma_input); + config.src_low = ADDRL(dma_input); + config.dst_high = ADDRH(dma_output); + config.dst_low = ADDRL(dma_output); + config.len_high = 0; + config.len_low = DMA_LEN; + DMA0CFGH = ADDRH(&config); + DMA0CFGL = ADDRL(&config); + for (i = 0; i < DMA_LEN; i++) + dma_input[i] = i + 1; +} + +void +dma_run(void) +{ + DMAREQ |= 1; + DMAARM |= 1; + while (DMAARM & 1) + ; +} + +main () +{ + int i; + P1DIR |= 2; + CLKCON = 0; + while (!(SLEEP & SLEEP_XOSC_STB)) + ; + + dma_init(); + dma_run(); + for (;;) { + for (i = 0; i < DMA_LEN; i++) + debug_byte(dma_output[i]); + } +} -- cgit v1.2.3 From d9fd548db15232e3a8823815962b252c7a5e7cba Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 10:04:50 -0700 Subject: Add ADC via DMA example --- target/adc/Makefile | 47 ++++++ target/adc/adc.c | 470 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 517 insertions(+) create mode 100644 target/adc/Makefile create mode 100644 target/adc/adc.c (limited to 'target') diff --git a/target/adc/Makefile b/target/adc/Makefile new file mode 100644 index 00000000..54c1211a --- /dev/null +++ b/target/adc/Makefile @@ -0,0 +1,47 @@ +PROG=adc +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse \ + --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large $(DEBUG) --less-pedantic \ + --no-peep --int-long-reent --float-reent \ + --data-loc 0x30 + +LDFLAGS=--out-fmt-ihx +LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf800 --xram-size 1024 + +LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 + +SRC=$(PROG).c +ADB=$(SRC:.c=.adb) +ASM=$(SRC:.c=.asm) +LNK=$(SRC:.c=.lnk) +LST=$(SRC:.c=.lst) +REL=$(SRC:.c=.rel) +RST=$(SRC:.c=.rst) +SYM=$(SRC:.c=.sym) + +PROGS=$(PROG)-flash.ihx $(PROG)-ram.ihx +PCDB=$(PROGS:.ihx=.cdb) +PLNK=$(PROGS:.ihx=.lnk) +PMAP=$(PROGS:.ihx=.map) +PMEM=$(PROGS:.ihx=.mem) +PAOM=$(PROGS:.ihx=) + +%.rel : %.c + $(CC) -c $(CFLAGS) -o$*.rel $< + +all: $(PROGS) + +$(PROG)-ram.ihx: $(REL) Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o $(PROG)-ram.ihx $(REL) + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o $(PROG)-flash.ihx $(REL) + +$(PROG)-flash.ihx: $(PROG)-ram.ihx + +clean: + rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) + rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) + +install: diff --git a/target/adc/adc.c b/target/adc/adc.c new file mode 100644 index 00000000..d6d15e6a --- /dev/null +++ b/target/adc/adc.c @@ -0,0 +1,470 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include + +/* + * Test ADC in DMA mode + */ + +sfr at 0x80 P0; +sfr at 0x90 P1; +sfr at 0xA0 P2; +sfr at 0xC6 CLKCON; +sfr at 0xbe SLEEP; + +# define SLEEP_USB_EN (1 << 7) +# define SLEEP_XOSC_STB (1 << 6) + +sfr at 0xF1 PERCFG; +#define PERCFG_T1CFG_ALT_1 (0 << 6) +#define PERCFG_T1CFG_ALT_2 (1 << 6) + +#define PERCFG_T3CFG_ALT_1 (0 << 5) +#define PERCFG_T3CFG_ALT_2 (1 << 5) + +#define PERCFG_T4CFG_ALT_1 (0 << 4) +#define PERCFG_T4CFG_ALT_2 (1 << 4) + +#define PERCFG_U1CFG_ALT_1 (0 << 1) +#define PERCFG_U1CFG_ALT_2 (1 << 1) + +#define PERCFG_U0CFG_ALT_1 (0 << 0) +#define PERCFG_U0CFG_ALT_2 (1 << 0) + +sfr at 0xF2 ADCCFG; +sfr at 0xF3 P0SEL; +sfr at 0xF4 P1SEL; +sfr at 0xF5 P2SEL; + +sfr at 0xFD P0DIR; +sfr at 0xFE P1DIR; +sfr at 0xFF P2DIR; +sfr at 0x8F P0INP; +sfr at 0xF6 P1INP; +sfr at 0xF7 P2INP; + +sfr at 0x89 P0IFG; +sfr at 0x8A P1IFG; +sfr at 0x8B P2IFG; + +sbit at 0x90 P1_0; +sbit at 0x91 P1_1; +sbit at 0x92 P1_2; +sbit at 0x93 P1_3; +sbit at 0x94 P1_4; +sbit at 0x95 P1_5; +sbit at 0x96 P1_6; +sbit at 0x97 P1_7; + +/* + * UART registers + */ + +sfr at 0x86 U0CSR; +sfr at 0xF8 U1CSR; + +/* + * IRCON2 + */ +sfr at 0xE8 IRCON2; /* CPU Interrupt Flag 5 */ + +sbit at 0xE8 USBIF; /* USB interrupt flag (shared with Port2) */ +sbit at 0xE8 P2IF; /* Port2 interrupt flag (shared with USB) */ +sbit at 0xE9 UTX0IF; /* USART0 TX interrupt flag */ +sbit at 0xEA UTX1IF; /* USART1 TX interrupt flag (shared with I2S TX) */ +sbit at 0xEA I2STXIF; /* I2S TX interrupt flag (shared with USART1 TX) */ +sbit at 0xEB P1IF; /* Port1 interrupt flag */ +sbit at 0xEC WDTIF; /* Watchdog timer interrupt flag */ + +# define UxCSR_MODE_UART (1 << 7) +# define UxCSR_MODE_SPI (0 << 7) +# define UxCSR_RE (1 << 6) +# define UxCSR_SLAVE (1 << 5) +# define UxCSR_MASTER (0 << 5) +# define UxCSR_FE (1 << 4) +# define UxCSR_ERR (1 << 3) +# define UxCSR_RX_BYTE (1 << 2) +# define UxCSR_TX_BYTE (1 << 1) +# define UxCSR_ACTIVE (1 << 0) + +sfr at 0xc4 U0UCR; +sfr at 0xfb U1UCR; + +# define UxUCR_FLUSH (1 << 7) +# define UxUCR_FLOW_DISABLE (0 << 6) +# define UxUCR_FLOW_ENABLE (1 << 6) +# define UxUCR_D9_EVEN_PARITY (0 << 5) +# define UxUCR_D9_ODD_PARITY (1 << 5) +# define UxUCR_BIT9_8_BITS (0 << 4) +# define UxUCR_BIT9_9_BITS (1 << 4) +# define UxUCR_PARITY_DISABLE (0 << 3) +# define UxUCR_PARITY_ENABLE (1 << 3) +# define UxUCR_SPB_1_STOP_BIT (0 << 2) +# define UxUCR_SPB_2_STOP_BITS (1 << 2) +# define UxUCR_STOP_LOW (0 << 1) +# define UxUCR_STOP_HIGH (1 << 1) +# define UxUCR_START_LOW (0 << 0) +# define UxUCR_START_HIGH (1 << 0) + +sfr at 0xc5 U0GCR; +sfr at 0xfc U1GCR; + +# define UxGCR_CPOL_NEGATIVE (0 << 7) +# define UxGCR_CPOL_POSITIVE (1 << 7) +# define UxGCR_CPHA_FIRST_EDGE (0 << 6) +# define UxGCR_CPHA_SECOND_EDGE (1 << 6) +# define UxGCR_ORDER_LSB (0 << 5) +# define UxGCR_ORDER_MSB (1 << 5) +# define UxGCR_BAUD_E_MASK (0x1f) +# define UxGCR_BAUD_E_SHIFT 0 + +sfr at 0xc1 U0DBUF; +sfr at 0xf9 U1DBUF; +sfr at 0xc2 U0BAUD; +sfr at 0xfa U1BAUD; + +#define DEBUG P1_1 + + +# define DMA_LEN_HIGH_VLEN_MASK (7 << 5) +# define DMA_LEN_HIGH_VLEN_LEN (0 << 5) +# define DMA_LEN_HIGH_VLEN_PLUS_1 (1 << 5) +# define DMA_LEN_HIGH_VLEN (2 << 5) +# define DMA_LEN_HIGH_VLEN_PLUS_2 (3 << 5) +# define DMA_LEN_HIGH_VLEN_PLUS_3 (4 << 5) +# define DMA_LEN_HIGH_MASK (0x1f) + +# define DMA_CFG0_WORDSIZE_8 (0 << 7) +# define DMA_CFG0_WORDSIZE_16 (1 << 7) +# define DMA_CFG0_TMODE_MASK (3 << 5) +# define DMA_CFG0_TMODE_SINGLE (0 << 5) +# define DMA_CFG0_TMODE_BLOCK (1 << 5) +# define DMA_CFG0_TMODE_REPEATED_SINGLE (2 << 5) +# define DMA_CFG0_TMODE_REPEATED_BLOCK (3 << 5) + +/* + * DMA triggers + */ +# define DMA_CFG0_TRIGGER_NONE 0 +# define DMA_CFG0_TRIGGER_PREV 1 +# define DMA_CFG0_TRIGGER_T1_CH0 2 +# define DMA_CFG0_TRIGGER_T1_CH1 3 +# define DMA_CFG0_TRIGGER_T1_CH2 4 +# define DMA_CFG0_TRIGGER_T2_OVFL 6 +# define DMA_CFG0_TRIGGER_T3_CH0 7 +# define DMA_CFG0_TRIGGER_T3_CH1 8 +# define DMA_CFG0_TRIGGER_T4_CH0 9 +# define DMA_CFG0_TRIGGER_T4_CH1 10 +# define DMA_CFG0_TRIGGER_IOC_0 12 +# define DMA_CFG0_TRIGGER_IOC_1 13 +# define DMA_CFG0_TRIGGER_URX0 14 +# define DMA_CFG0_TRIGGER_UTX0 15 +# define DMA_CFG0_TRIGGER_URX1 16 +# define DMA_CFG0_TRIGGER_UTX1 17 +# define DMA_CFG0_TRIGGER_FLASH 18 +# define DMA_CFG0_TRIGGER_RADIO 19 +# define DMA_CFG0_TRIGGER_ADC_CHALL 20 +# define DMA_CFG0_TRIGGER_ADC_CH0 21 +# define DMA_CFG0_TRIGGER_ADC_CH1 22 +# define DMA_CFG0_TRIGGER_ADC_CH2 23 +# define DMA_CFG0_TRIGGER_ADC_CH3 24 +# define DMA_CFG0_TRIGGER_ADC_CH4 25 +# define DMA_CFG0_TRIGGER_ADC_CH5 26 +# define DMA_CFG0_TRIGGER_ADC_CH6 27 +# define DMA_CFG0_TRIGGER_I2SRX 27 +# define DMA_CFG0_TRIGGER_ADC_CH7 28 +# define DMA_CFG0_TRIGGER_I2STX 28 +# define DMA_CFG0_TRIGGER_ENC_DW 29 +# define DMA_CFG0_TRIGGER_DNC_UP 30 + +# define DMA_CFG1_SRCINC_MASK (3 << 6) +# define DMA_CFG1_SRCINC_0 (0 << 6) +# define DMA_CFG1_SRCINC_1 (1 << 6) +# define DMA_CFG1_SRCINC_2 (2 << 6) +# define DMA_CFG1_SRCINC_MINUS_1 (3 << 6) + +# define DMA_CFG1_DESTINC_MASK (3 << 4) +# define DMA_CFG1_DESTINC_0 (0 << 4) +# define DMA_CFG1_DESTINC_1 (1 << 4) +# define DMA_CFG1_DESTINC_2 (2 << 4) +# define DMA_CFG1_DESTINC_MINUS_1 (3 << 4) + +# define DMA_CFG1_IRQMASK (1 << 3) +# define DMA_CFG1_M8 (1 << 2) + +# define DMA_CFG1_PRIORITY_MASK (3 << 0) +# define DMA_CFG1_PRIORITY_LOW (0 << 0) +# define DMA_CFG1_PRIORITY_NORMAL (1 << 0) +# define DMA_CFG1_PRIORITY_HIGH (2 << 0) + +/* + * DMAARM - DMA Channel Arm + */ + +sfr at 0xD6 DMAARM; + +# define DMAARM_ABORT (1 << 7) +# define DMAARM_DMAARM4 (1 << 4) +# define DMAARM_DMAARM3 (1 << 3) +# define DMAARM_DMAARM2 (1 << 2) +# define DMAARM_DMAARM1 (1 << 1) +# define DMAARM_DMAARM0 (1 << 0) + +/* + * DMAREQ - DMA Channel Start Request and Status + */ + +sfr at 0xD7 DMAREQ; + +# define DMAREQ_DMAREQ4 (1 << 4) +# define DMAREQ_DMAREQ3 (1 << 3) +# define DMAREQ_DMAREQ2 (1 << 2) +# define DMAREQ_DMAREQ1 (1 << 1) +# define DMAREQ_DMAREQ0 (1 << 0) + +/* + * DMA configuration 0 address + */ + +sfr at 0xD5 DMA0CFGH; +sfr at 0xD4 DMA0CFGL; + +/* + * DMA configuration 1-4 address + */ + +sfr at 0xD3 DMA1CFGH; +sfr at 0xD2 DMA1CFGL; + +/* + * DMAIRQ - DMA Interrupt Flag + */ + +sfr at 0xD1 DMAIRQ; + +# define DMAIRQ_DMAIF4 (1 << 4) +# define DMAIRQ_DMAIF3 (1 << 3) +# define DMAIRQ_DMAIF2 (1 << 2) +# define DMAIRQ_DMAIF1 (1 << 1) +# define DMAIRQ_DMAIF0 (1 << 0) + +struct cc_dma_channel { + uint8_t src_high; + uint8_t src_low; + uint8_t dst_high; + uint8_t dst_low; + uint8_t len_high; + uint8_t len_low; + uint8_t cfg0; + uint8_t cfg1; +}; + +/* + * ADC Data register, low and high + */ +sfr at 0xBA ADCL; +sfr at 0xBB ADCH; +__xdata __at (0xDFBA) volatile uint16_t ADCXDATA; + +/* + * ADC Control Register 1 + */ +sfr at 0xB4 ADCCON1; + +# define ADCCON1_EOC (1 << 7) /* conversion complete */ +# define ADCCON1_ST (1 << 6) /* start conversion */ + +# define ADCCON1_STSEL_MASK (3 << 4) /* start select */ +# define ADCCON1_STSEL_EXTERNAL (0 << 4) /* P2_0 pin triggers */ +# define ADCCON1_STSEL_FULLSPEED (1 << 4) /* full speed, no waiting */ +# define ADCCON1_STSEL_TIMER1 (2 << 4) /* timer 1 channel 0 */ +# define ADCCON1_STSEL_START (3 << 4) /* set start bit */ + +# define ADCCON1_RCTRL_MASK (3 << 2) /* random number control */ +# define ADCCON1_RCTRL_COMPLETE (0 << 2) /* operation completed */ +# define ADCCON1_RCTRL_CLOCK_LFSR (1 << 2) /* Clock the LFSR once */ + +/* + * ADC Control Register 2 + */ +sfr at 0xB5 ADCCON2; + +# define ADCCON2_SREF_MASK (3 << 6) /* reference voltage */ +# define ADCCON2_SREF_1_25V (0 << 6) /* internal 1.25V */ +# define ADCCON2_SREF_EXTERNAL (1 << 6) /* external on AIN7 cc1110 */ +# define ADCCON2_SREF_VDD (2 << 6) /* VDD on the AVDD pin */ +# define ADCCON2_SREF_EXTERNAL_DIFF (3 << 6) /* external on AIN6-7 cc1110 */ + +# define ADCCON2_SDIV_MASK (3 << 4) /* decimation rate */ +# define ADCCON2_SDIV_64 (0 << 4) /* 7 bits */ +# define ADCCON2_SDIV_128 (1 << 4) /* 9 bits */ +# define ADCCON2_SDIV_256 (2 << 4) /* 10 bits */ +# define ADCCON2_SDIV_512 (3 << 4) /* 12 bits */ + +# define ADCCON2_SCH_MASK (0xf << 0) /* Sequence channel select */ +# define ADCCON2_SCH_SHIFT 0 +# define ADCCON2_SCH_AIN0 (0 << 0) +# define ADCCON2_SCH_AIN1 (1 << 0) +# define ADCCON2_SCH_AIN2 (2 << 0) +# define ADCCON2_SCH_AIN3 (3 << 0) +# define ADCCON2_SCH_AIN4 (4 << 0) +# define ADCCON2_SCH_AIN5 (5 << 0) +# define ADCCON2_SCH_AIN6 (6 << 0) +# define ADCCON2_SCH_AIN7 (7 << 0) +# define ADCCON2_SCH_AIN0_AIN1 (8 << 0) +# define ADCCON2_SCH_AIN2_AIN3 (9 << 0) +# define ADCCON2_SCH_AIN4_AIN5 (0xa << 0) +# define ADCCON2_SCH_AIN6_AIN7 (0xb << 0) +# define ADCCON2_SCH_GND (0xc << 0) +# define ADCCON2_SCH_VREF (0xd << 0) +# define ADCCON2_SCH_TEMP (0xe << 0) +# define ADCCON2_SCH_VDD_3 (0xf << 0) + + +/* + * ADC Control Register 3 + */ + +sfr at 0xB6 ADCCON3; + +# define ADCCON3_EREF_MASK (3 << 6) /* extra conversion reference */ +# define ADCCON3_EREF_1_25 (0 << 6) /* internal 1.25V */ +# define ADCCON3_EREF_EXTERNAL (1 << 6) /* external AIN7 cc1110 */ +# define ADCCON3_EREF_VDD (2 << 6) /* VDD on the AVDD pin */ +# define ADCCON3_EREF_EXTERNAL_DIFF (3 << 6) /* external AIN6-7 cc1110 */ +# define ADCCON2_EDIV_MASK (3 << 4) /* extral decimation */ +# define ADCCON2_EDIV_64 (0 << 4) /* 7 bits */ +# define ADCCON2_EDIV_128 (1 << 4) /* 9 bits */ +# define ADCCON2_EDIV_256 (2 << 4) /* 10 bits */ +# define ADCCON2_EDIV_512 (3 << 4) /* 12 bits */ +# define ADCCON3_ECH_MASK (0xf << 0) /* Sequence channel select */ +# define ADCCON3_ECH_SHIFT 0 +# define ADCCON3_ECH_AIN0 (0 << 0) +# define ADCCON3_ECH_AIN1 (1 << 0) +# define ADCCON3_ECH_AIN2 (2 << 0) +# define ADCCON3_ECH_AIN3 (3 << 0) +# define ADCCON3_ECH_AIN4 (4 << 0) +# define ADCCON3_ECH_AIN5 (5 << 0) +# define ADCCON3_ECH_AIN6 (6 << 0) +# define ADCCON3_ECH_AIN7 (7 << 0) +# define ADCCON3_ECH_AIN0_AIN1 (8 << 0) +# define ADCCON3_ECH_AIN2_AIN3 (9 << 0) +# define ADCCON3_ECH_AIN4_AIN5 (0xa << 0) +# define ADCCON3_ECH_AIN6_AIN7 (0xb << 0) +# define ADCCON3_ECH_GND (0xc << 0) +# define ADCCON3_ECH_VREF (0xd << 0) +# define ADCCON3_ECH_TEMP (0xe << 0) +# define ADCCON3_ECH_VDD_3 (0xf << 0) + +sfr at 0xF2 ADCCFG; + +#define nop() _asm nop _endasm; + +void +delay (unsigned char n) +{ + unsigned char i = 0; + unsigned char j = 0; + + n++; + while (--n != 0) + while (--i != 0) + while (--j != 0) + nop(); +} + +void +debug_byte(uint8_t byte) +{ + uint8_t s; + + for (s = 0; s < 8; s++) { + DEBUG = byte & 1; + delay(5); + byte >>= 1; + } +} + +struct cc_dma_channel __xdata dma_config; + +#define ADC_LEN 6 + +uint16_t __xdata adc_output[ADC_LEN]; + +#define ADDRH(a) (((uint16_t) (a)) >> 8) +#define ADDRL(a) (((uint16_t) (a))) + +void +adc_init(void) +{ + dma_config.cfg0 = (DMA_CFG0_WORDSIZE_16 | + DMA_CFG0_TMODE_REPEATED_SINGLE | + DMA_CFG0_TRIGGER_ADC_CHALL); + dma_config.cfg1 = (DMA_CFG1_SRCINC_0 | + DMA_CFG1_DESTINC_2 | + DMA_CFG1_PRIORITY_NORMAL); + + dma_config.src_high = ADDRH(&ADCXDATA); + dma_config.src_low = ADDRL(&ADCXDATA); + dma_config.dst_high = ADDRH(adc_output); + dma_config.dst_low = ADDRL(adc_output); + dma_config.len_high = 0; + dma_config.len_low = ADC_LEN; + DMA0CFGH = ADDRH(&dma_config); + DMA0CFGL = ADDRL(&dma_config); + ADCCFG = ((1 << 0) | /* acceleration */ + (1 << 1) | /* pressure */ + (1 << 2) | /* temperature */ + (1 << 3) | /* battery voltage */ + (1 << 4) | /* drogue sense */ + (1 << 5)); /* main sense */ + + ADCCON1 = (ADCCON1_STSEL_START); /* ST bit triggers */ + ADCCON2 = (ADCCON2_SREF_VDD | /* reference voltage is VDD */ + ADCCON2_SDIV_512 | /* 12 bit ADC results */ + ADCCON2_SCH_AIN5); /* sample all 6 inputs */ +} + +void +adc_run(void) +{ + DMAIRQ &= ~1; + DMAARM |= 1; + ADCCON1 |= ADCCON1_ST; + while ((DMAIRQ & 1) == 0) + ; +} + +main () +{ + int i; + P1DIR |= 2; + CLKCON = 0; + while (!(SLEEP & SLEEP_XOSC_STB)) + ; + while (P1 & 0x4) + ; + + adc_init(); + for (;;) { + adc_run(); + for (i = 0; i < ADC_LEN; i++) + debug_byte(adc_output[i]); + } +} -- cgit v1.2.3 From 2b93a70fdd9e47e8195855451aa19ecad5d8b068 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 10:50:14 -0700 Subject: Add adc to serial conversion --- target/adc-serial/Makefile | 47 ++++ target/adc-serial/adc_serial.c | 557 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 604 insertions(+) create mode 100644 target/adc-serial/Makefile create mode 100644 target/adc-serial/adc_serial.c (limited to 'target') diff --git a/target/adc-serial/Makefile b/target/adc-serial/Makefile new file mode 100644 index 00000000..9a8bf5c6 --- /dev/null +++ b/target/adc-serial/Makefile @@ -0,0 +1,47 @@ +PROG=adc_serial +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse \ + --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large $(DEBUG) --stack-auto --less-pedantic \ + --no-peep --int-long-reent --float-reent \ + --data-loc 0x30 + +LDFLAGS=--out-fmt-ihx +LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf800 --xram-size 1024 + +LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 + +SRC=$(PROG).c +ADB=$(SRC:.c=.adb) +ASM=$(SRC:.c=.asm) +LNK=$(SRC:.c=.lnk) +LST=$(SRC:.c=.lst) +REL=$(SRC:.c=.rel) +RST=$(SRC:.c=.rst) +SYM=$(SRC:.c=.sym) + +PROGS=$(PROG)-flash.ihx $(PROG)-ram.ihx +PCDB=$(PROGS:.ihx=.cdb) +PLNK=$(PROGS:.ihx=.lnk) +PMAP=$(PROGS:.ihx=.map) +PMEM=$(PROGS:.ihx=.mem) +PAOM=$(PROGS:.ihx=) + +%.rel : %.c + $(CC) -c $(CFLAGS) -o$*.rel $< + +all: $(PROGS) + +$(PROG)-ram.ihx: $(REL) Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o $(PROG)-ram.ihx $(REL) + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o $(PROG)-flash.ihx $(REL) + +$(PROG)-flash.ihx: $(PROG)-ram.ihx + +clean: + rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) + rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) + +install: diff --git a/target/adc-serial/adc_serial.c b/target/adc-serial/adc_serial.c new file mode 100644 index 00000000..c141567a --- /dev/null +++ b/target/adc-serial/adc_serial.c @@ -0,0 +1,557 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include + +/* + * Test ADC in DMA mode + */ + +sfr at 0x80 P0; +sfr at 0x90 P1; +sfr at 0xA0 P2; +sfr at 0xC6 CLKCON; +sfr at 0xbe SLEEP; + +# define SLEEP_USB_EN (1 << 7) +# define SLEEP_XOSC_STB (1 << 6) + +sfr at 0xF1 PERCFG; +#define PERCFG_T1CFG_ALT_1 (0 << 6) +#define PERCFG_T1CFG_ALT_2 (1 << 6) + +#define PERCFG_T3CFG_ALT_1 (0 << 5) +#define PERCFG_T3CFG_ALT_2 (1 << 5) + +#define PERCFG_T4CFG_ALT_1 (0 << 4) +#define PERCFG_T4CFG_ALT_2 (1 << 4) + +#define PERCFG_U1CFG_ALT_1 (0 << 1) +#define PERCFG_U1CFG_ALT_2 (1 << 1) + +#define PERCFG_U0CFG_ALT_1 (0 << 0) +#define PERCFG_U0CFG_ALT_2 (1 << 0) + +sfr at 0xF2 ADCCFG; +sfr at 0xF3 P0SEL; +sfr at 0xF4 P1SEL; +sfr at 0xF5 P2SEL; + +sfr at 0xFD P0DIR; +sfr at 0xFE P1DIR; +sfr at 0xFF P2DIR; +sfr at 0x8F P0INP; +sfr at 0xF6 P1INP; +sfr at 0xF7 P2INP; + +sfr at 0x89 P0IFG; +sfr at 0x8A P1IFG; +sfr at 0x8B P2IFG; + +sbit at 0x90 P1_0; +sbit at 0x91 P1_1; +sbit at 0x92 P1_2; +sbit at 0x93 P1_3; +sbit at 0x94 P1_4; +sbit at 0x95 P1_5; +sbit at 0x96 P1_6; +sbit at 0x97 P1_7; + +/* + * UART registers + */ + +sfr at 0x86 U0CSR; +sfr at 0xF8 U1CSR; + +/* + * IRCON2 + */ +sfr at 0xE8 IRCON2; /* CPU Interrupt Flag 5 */ + +sbit at 0xE8 USBIF; /* USB interrupt flag (shared with Port2) */ +sbit at 0xE8 P2IF; /* Port2 interrupt flag (shared with USB) */ +sbit at 0xE9 UTX0IF; /* USART0 TX interrupt flag */ +sbit at 0xEA UTX1IF; /* USART1 TX interrupt flag (shared with I2S TX) */ +sbit at 0xEA I2STXIF; /* I2S TX interrupt flag (shared with USART1 TX) */ +sbit at 0xEB P1IF; /* Port1 interrupt flag */ +sbit at 0xEC WDTIF; /* Watchdog timer interrupt flag */ + +# define UxCSR_MODE_UART (1 << 7) +# define UxCSR_MODE_SPI (0 << 7) +# define UxCSR_RE (1 << 6) +# define UxCSR_SLAVE (1 << 5) +# define UxCSR_MASTER (0 << 5) +# define UxCSR_FE (1 << 4) +# define UxCSR_ERR (1 << 3) +# define UxCSR_RX_BYTE (1 << 2) +# define UxCSR_TX_BYTE (1 << 1) +# define UxCSR_ACTIVE (1 << 0) + +sfr at 0xc4 U0UCR; +sfr at 0xfb U1UCR; + +# define UxUCR_FLUSH (1 << 7) +# define UxUCR_FLOW_DISABLE (0 << 6) +# define UxUCR_FLOW_ENABLE (1 << 6) +# define UxUCR_D9_EVEN_PARITY (0 << 5) +# define UxUCR_D9_ODD_PARITY (1 << 5) +# define UxUCR_BIT9_8_BITS (0 << 4) +# define UxUCR_BIT9_9_BITS (1 << 4) +# define UxUCR_PARITY_DISABLE (0 << 3) +# define UxUCR_PARITY_ENABLE (1 << 3) +# define UxUCR_SPB_1_STOP_BIT (0 << 2) +# define UxUCR_SPB_2_STOP_BITS (1 << 2) +# define UxUCR_STOP_LOW (0 << 1) +# define UxUCR_STOP_HIGH (1 << 1) +# define UxUCR_START_LOW (0 << 0) +# define UxUCR_START_HIGH (1 << 0) + +sfr at 0xc5 U0GCR; +sfr at 0xfc U1GCR; + +# define UxGCR_CPOL_NEGATIVE (0 << 7) +# define UxGCR_CPOL_POSITIVE (1 << 7) +# define UxGCR_CPHA_FIRST_EDGE (0 << 6) +# define UxGCR_CPHA_SECOND_EDGE (1 << 6) +# define UxGCR_ORDER_LSB (0 << 5) +# define UxGCR_ORDER_MSB (1 << 5) +# define UxGCR_BAUD_E_MASK (0x1f) +# define UxGCR_BAUD_E_SHIFT 0 + +sfr at 0xc1 U0DBUF; +sfr at 0xf9 U1DBUF; +sfr at 0xc2 U0BAUD; +sfr at 0xfa U1BAUD; + +#define DEBUG P1_1 + + +# define DMA_LEN_HIGH_VLEN_MASK (7 << 5) +# define DMA_LEN_HIGH_VLEN_LEN (0 << 5) +# define DMA_LEN_HIGH_VLEN_PLUS_1 (1 << 5) +# define DMA_LEN_HIGH_VLEN (2 << 5) +# define DMA_LEN_HIGH_VLEN_PLUS_2 (3 << 5) +# define DMA_LEN_HIGH_VLEN_PLUS_3 (4 << 5) +# define DMA_LEN_HIGH_MASK (0x1f) + +# define DMA_CFG0_WORDSIZE_8 (0 << 7) +# define DMA_CFG0_WORDSIZE_16 (1 << 7) +# define DMA_CFG0_TMODE_MASK (3 << 5) +# define DMA_CFG0_TMODE_SINGLE (0 << 5) +# define DMA_CFG0_TMODE_BLOCK (1 << 5) +# define DMA_CFG0_TMODE_REPEATED_SINGLE (2 << 5) +# define DMA_CFG0_TMODE_REPEATED_BLOCK (3 << 5) + +/* + * DMA triggers + */ +# define DMA_CFG0_TRIGGER_NONE 0 +# define DMA_CFG0_TRIGGER_PREV 1 +# define DMA_CFG0_TRIGGER_T1_CH0 2 +# define DMA_CFG0_TRIGGER_T1_CH1 3 +# define DMA_CFG0_TRIGGER_T1_CH2 4 +# define DMA_CFG0_TRIGGER_T2_OVFL 6 +# define DMA_CFG0_TRIGGER_T3_CH0 7 +# define DMA_CFG0_TRIGGER_T3_CH1 8 +# define DMA_CFG0_TRIGGER_T4_CH0 9 +# define DMA_CFG0_TRIGGER_T4_CH1 10 +# define DMA_CFG0_TRIGGER_IOC_0 12 +# define DMA_CFG0_TRIGGER_IOC_1 13 +# define DMA_CFG0_TRIGGER_URX0 14 +# define DMA_CFG0_TRIGGER_UTX0 15 +# define DMA_CFG0_TRIGGER_URX1 16 +# define DMA_CFG0_TRIGGER_UTX1 17 +# define DMA_CFG0_TRIGGER_FLASH 18 +# define DMA_CFG0_TRIGGER_RADIO 19 +# define DMA_CFG0_TRIGGER_ADC_CHALL 20 +# define DMA_CFG0_TRIGGER_ADC_CH0 21 +# define DMA_CFG0_TRIGGER_ADC_CH1 22 +# define DMA_CFG0_TRIGGER_ADC_CH2 23 +# define DMA_CFG0_TRIGGER_ADC_CH3 24 +# define DMA_CFG0_TRIGGER_ADC_CH4 25 +# define DMA_CFG0_TRIGGER_ADC_CH5 26 +# define DMA_CFG0_TRIGGER_ADC_CH6 27 +# define DMA_CFG0_TRIGGER_I2SRX 27 +# define DMA_CFG0_TRIGGER_ADC_CH7 28 +# define DMA_CFG0_TRIGGER_I2STX 28 +# define DMA_CFG0_TRIGGER_ENC_DW 29 +# define DMA_CFG0_TRIGGER_DNC_UP 30 + +# define DMA_CFG1_SRCINC_MASK (3 << 6) +# define DMA_CFG1_SRCINC_0 (0 << 6) +# define DMA_CFG1_SRCINC_1 (1 << 6) +# define DMA_CFG1_SRCINC_2 (2 << 6) +# define DMA_CFG1_SRCINC_MINUS_1 (3 << 6) + +# define DMA_CFG1_DESTINC_MASK (3 << 4) +# define DMA_CFG1_DESTINC_0 (0 << 4) +# define DMA_CFG1_DESTINC_1 (1 << 4) +# define DMA_CFG1_DESTINC_2 (2 << 4) +# define DMA_CFG1_DESTINC_MINUS_1 (3 << 4) + +# define DMA_CFG1_IRQMASK (1 << 3) +# define DMA_CFG1_M8 (1 << 2) + +# define DMA_CFG1_PRIORITY_MASK (3 << 0) +# define DMA_CFG1_PRIORITY_LOW (0 << 0) +# define DMA_CFG1_PRIORITY_NORMAL (1 << 0) +# define DMA_CFG1_PRIORITY_HIGH (2 << 0) + +/* + * DMAARM - DMA Channel Arm + */ + +sfr at 0xD6 DMAARM; + +# define DMAARM_ABORT (1 << 7) +# define DMAARM_DMAARM4 (1 << 4) +# define DMAARM_DMAARM3 (1 << 3) +# define DMAARM_DMAARM2 (1 << 2) +# define DMAARM_DMAARM1 (1 << 1) +# define DMAARM_DMAARM0 (1 << 0) + +/* + * DMAREQ - DMA Channel Start Request and Status + */ + +sfr at 0xD7 DMAREQ; + +# define DMAREQ_DMAREQ4 (1 << 4) +# define DMAREQ_DMAREQ3 (1 << 3) +# define DMAREQ_DMAREQ2 (1 << 2) +# define DMAREQ_DMAREQ1 (1 << 1) +# define DMAREQ_DMAREQ0 (1 << 0) + +/* + * DMA configuration 0 address + */ + +sfr at 0xD5 DMA0CFGH; +sfr at 0xD4 DMA0CFGL; + +/* + * DMA configuration 1-4 address + */ + +sfr at 0xD3 DMA1CFGH; +sfr at 0xD2 DMA1CFGL; + +/* + * DMAIRQ - DMA Interrupt Flag + */ + +sfr at 0xD1 DMAIRQ; + +# define DMAIRQ_DMAIF4 (1 << 4) +# define DMAIRQ_DMAIF3 (1 << 3) +# define DMAIRQ_DMAIF2 (1 << 2) +# define DMAIRQ_DMAIF1 (1 << 1) +# define DMAIRQ_DMAIF0 (1 << 0) + +struct cc_dma_channel { + uint8_t src_high; + uint8_t src_low; + uint8_t dst_high; + uint8_t dst_low; + uint8_t len_high; + uint8_t len_low; + uint8_t cfg0; + uint8_t cfg1; +}; + +/* + * ADC Data register, low and high + */ +sfr at 0xBA ADCL; +sfr at 0xBB ADCH; +__xdata __at (0xDFBA) volatile uint16_t ADCXDATA; + +/* + * ADC Control Register 1 + */ +sfr at 0xB4 ADCCON1; + +# define ADCCON1_EOC (1 << 7) /* conversion complete */ +# define ADCCON1_ST (1 << 6) /* start conversion */ + +# define ADCCON1_STSEL_MASK (3 << 4) /* start select */ +# define ADCCON1_STSEL_EXTERNAL (0 << 4) /* P2_0 pin triggers */ +# define ADCCON1_STSEL_FULLSPEED (1 << 4) /* full speed, no waiting */ +# define ADCCON1_STSEL_TIMER1 (2 << 4) /* timer 1 channel 0 */ +# define ADCCON1_STSEL_START (3 << 4) /* set start bit */ + +# define ADCCON1_RCTRL_MASK (3 << 2) /* random number control */ +# define ADCCON1_RCTRL_COMPLETE (0 << 2) /* operation completed */ +# define ADCCON1_RCTRL_CLOCK_LFSR (1 << 2) /* Clock the LFSR once */ + +/* + * ADC Control Register 2 + */ +sfr at 0xB5 ADCCON2; + +# define ADCCON2_SREF_MASK (3 << 6) /* reference voltage */ +# define ADCCON2_SREF_1_25V (0 << 6) /* internal 1.25V */ +# define ADCCON2_SREF_EXTERNAL (1 << 6) /* external on AIN7 cc1110 */ +# define ADCCON2_SREF_VDD (2 << 6) /* VDD on the AVDD pin */ +# define ADCCON2_SREF_EXTERNAL_DIFF (3 << 6) /* external on AIN6-7 cc1110 */ + +# define ADCCON2_SDIV_MASK (3 << 4) /* decimation rate */ +# define ADCCON2_SDIV_64 (0 << 4) /* 7 bits */ +# define ADCCON2_SDIV_128 (1 << 4) /* 9 bits */ +# define ADCCON2_SDIV_256 (2 << 4) /* 10 bits */ +# define ADCCON2_SDIV_512 (3 << 4) /* 12 bits */ + +# define ADCCON2_SCH_MASK (0xf << 0) /* Sequence channel select */ +# define ADCCON2_SCH_SHIFT 0 +# define ADCCON2_SCH_AIN0 (0 << 0) +# define ADCCON2_SCH_AIN1 (1 << 0) +# define ADCCON2_SCH_AIN2 (2 << 0) +# define ADCCON2_SCH_AIN3 (3 << 0) +# define ADCCON2_SCH_AIN4 (4 << 0) +# define ADCCON2_SCH_AIN5 (5 << 0) +# define ADCCON2_SCH_AIN6 (6 << 0) +# define ADCCON2_SCH_AIN7 (7 << 0) +# define ADCCON2_SCH_AIN0_AIN1 (8 << 0) +# define ADCCON2_SCH_AIN2_AIN3 (9 << 0) +# define ADCCON2_SCH_AIN4_AIN5 (0xa << 0) +# define ADCCON2_SCH_AIN6_AIN7 (0xb << 0) +# define ADCCON2_SCH_GND (0xc << 0) +# define ADCCON2_SCH_VREF (0xd << 0) +# define ADCCON2_SCH_TEMP (0xe << 0) +# define ADCCON2_SCH_VDD_3 (0xf << 0) + + +/* + * ADC Control Register 3 + */ + +sfr at 0xB6 ADCCON3; + +# define ADCCON3_EREF_MASK (3 << 6) /* extra conversion reference */ +# define ADCCON3_EREF_1_25 (0 << 6) /* internal 1.25V */ +# define ADCCON3_EREF_EXTERNAL (1 << 6) /* external AIN7 cc1110 */ +# define ADCCON3_EREF_VDD (2 << 6) /* VDD on the AVDD pin */ +# define ADCCON3_EREF_EXTERNAL_DIFF (3 << 6) /* external AIN6-7 cc1110 */ +# define ADCCON2_EDIV_MASK (3 << 4) /* extral decimation */ +# define ADCCON2_EDIV_64 (0 << 4) /* 7 bits */ +# define ADCCON2_EDIV_128 (1 << 4) /* 9 bits */ +# define ADCCON2_EDIV_256 (2 << 4) /* 10 bits */ +# define ADCCON2_EDIV_512 (3 << 4) /* 12 bits */ +# define ADCCON3_ECH_MASK (0xf << 0) /* Sequence channel select */ +# define ADCCON3_ECH_SHIFT 0 +# define ADCCON3_ECH_AIN0 (0 << 0) +# define ADCCON3_ECH_AIN1 (1 << 0) +# define ADCCON3_ECH_AIN2 (2 << 0) +# define ADCCON3_ECH_AIN3 (3 << 0) +# define ADCCON3_ECH_AIN4 (4 << 0) +# define ADCCON3_ECH_AIN5 (5 << 0) +# define ADCCON3_ECH_AIN6 (6 << 0) +# define ADCCON3_ECH_AIN7 (7 << 0) +# define ADCCON3_ECH_AIN0_AIN1 (8 << 0) +# define ADCCON3_ECH_AIN2_AIN3 (9 << 0) +# define ADCCON3_ECH_AIN4_AIN5 (0xa << 0) +# define ADCCON3_ECH_AIN6_AIN7 (0xb << 0) +# define ADCCON3_ECH_GND (0xc << 0) +# define ADCCON3_ECH_VREF (0xd << 0) +# define ADCCON3_ECH_TEMP (0xe << 0) +# define ADCCON3_ECH_VDD_3 (0xf << 0) + +sfr at 0xF2 ADCCFG; + +#define nop() _asm nop _endasm; + +void +delay (unsigned char n) +{ + unsigned char i = 0; + unsigned char j = 0; + + n++; + while (--n != 0) + while (--i != 0) + while (--j != 0) + nop(); +} + +void +debug_byte(uint8_t byte) +{ + uint8_t s; + + for (s = 0; s < 8; s++) { + DEBUG = byte & 1; + delay(5); + byte >>= 1; + } +} + +struct cc_dma_channel __xdata dma_config; + +#define ADC_LEN 6 + +uint16_t __xdata adc_output[ADC_LEN]; + +#define ADDRH(a) (((uint16_t) (a)) >> 8) +#define ADDRL(a) (((uint16_t) (a))) + +void +adc_init(void) +{ + dma_config.cfg0 = (DMA_CFG0_WORDSIZE_16 | + DMA_CFG0_TMODE_REPEATED_SINGLE | + DMA_CFG0_TRIGGER_ADC_CHALL); + dma_config.cfg1 = (DMA_CFG1_SRCINC_0 | + DMA_CFG1_DESTINC_2 | + DMA_CFG1_PRIORITY_NORMAL); + + dma_config.src_high = ADDRH(&ADCXDATA); + dma_config.src_low = ADDRL(&ADCXDATA); + dma_config.dst_high = ADDRH(adc_output); + dma_config.dst_low = ADDRL(adc_output); + dma_config.len_high = 0; + dma_config.len_low = ADC_LEN; + DMA0CFGH = ADDRH(&dma_config); + DMA0CFGL = ADDRL(&dma_config); + ADCCFG = ((1 << 0) | /* acceleration */ + (1 << 1) | /* pressure */ + (1 << 2) | /* temperature */ + (1 << 3) | /* battery voltage */ + (1 << 4) | /* drogue sense */ + (1 << 5)); /* main sense */ + + ADCCON1 = (ADCCON1_STSEL_START); /* ST bit triggers */ + ADCCON2 = (ADCCON2_SREF_VDD | /* reference voltage is VDD */ + ADCCON2_SDIV_512 | /* 12 bit ADC results */ + ADCCON2_SCH_AIN5); /* sample all 6 inputs */ +} + +void +adc_run(void) +{ + DMAIRQ &= ~1; + DMAARM |= 1; + ADCCON1 |= ADCCON1_ST; + while ((DMAIRQ & 1) == 0) + ; +} + +/* + * This version uses the USART in UART mode + */ +void +usart_init(void) +{ + P1DIR |= (1 << 2); + /* + * Configure the peripheral pin choices + * for both of the serial ports + * + * Note that telemetrum will use U1CFG_ALT_2 + * but that overlaps with SPI ALT_2, so until + * we can test that this works, we'll set this + * to ALT_1 + */ + PERCFG = (PERCFG_U1CFG_ALT_2 | + PERCFG_U0CFG_ALT_1); + + /* + * Make the UART pins controlled by the UART + * hardware + */ + P1SEL |= ((1 << 6) | (1 << 7)); + + /* + * UART mode with the receiver enabled + */ + U1CSR = (UxCSR_MODE_UART | + UxCSR_RE); + /* + * Pick a 38.4kbaud rate + */ + U1BAUD = 163; + U1GCR = 10 << UxGCR_BAUD_E_SHIFT; /* 38400 */ +// U1GCR = 3 << UxGCR_BAUD_E_SHIFT; /* 300 */ + /* + * Reasonable serial parameters + */ + U1UCR = (UxUCR_FLUSH | + UxUCR_FLOW_DISABLE | + UxUCR_D9_ODD_PARITY | + UxUCR_BIT9_8_BITS | + UxUCR_PARITY_DISABLE | + UxUCR_SPB_2_STOP_BITS | + UxUCR_STOP_HIGH | + UxUCR_START_LOW); +} + +void +usart_out_byte(uint8_t byte) +{ + U1DBUF = byte; + while (!UTX1IF) + ; + UTX1IF = 0; +} + +void +usart_out_string(uint8_t *string) +{ + uint8_t b; + + while (b = *string++) + usart_out_byte(b); +} + +uint8_t __xdata num_buffer[10]; +uint8_t __xdata * __xdata num_ptr; + +void +usart_out_number(uint16_t v) +{ + + num_ptr = num_buffer + 10; + *--num_ptr = '\0'; + do { + *--num_ptr = '0' + v % 10; + v /= 10; + } while (v); + usart_out_string(num_ptr); +} + +main () +{ + P1DIR |= 2; + CLKCON = 0; + while (!(SLEEP & SLEEP_XOSC_STB)) + ; + while (P1 & 0x4) + ; + + adc_init(); + usart_init(); + for (;;) { + adc_run(); + usart_out_string("drogue: "); + usart_out_number(adc_output[4]); + usart_out_string(" main: "); + usart_out_number(adc_output[5]); + usart_out_string("\r\n"); + delay(10); + } +} -- cgit v1.2.3 From f54a41e37d6897db2e24fbc82880076b78a0ae41 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 10:50:36 -0700 Subject: Remove poll for ti demo button --- target/adc-serial/adc_serial.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'target') diff --git a/target/adc-serial/adc_serial.c b/target/adc-serial/adc_serial.c index c141567a..d10b3f79 100644 --- a/target/adc-serial/adc_serial.c +++ b/target/adc-serial/adc_serial.c @@ -540,8 +540,6 @@ main () CLKCON = 0; while (!(SLEEP & SLEEP_XOSC_STB)) ; - while (P1 & 0x4) - ; adc_init(); usart_init(); -- cgit v1.2.3 From 378227d869a3e8787c532c8c4e1563b44002c4b5 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 10:55:17 -0700 Subject: Dump remaining inputs --- target/adc-serial/adc_serial.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'target') diff --git a/target/adc-serial/adc_serial.c b/target/adc-serial/adc_serial.c index d10b3f79..349f3d7e 100644 --- a/target/adc-serial/adc_serial.c +++ b/target/adc-serial/adc_serial.c @@ -545,6 +545,14 @@ main () usart_init(); for (;;) { adc_run(); + usart_out_string("accel: "); + usart_out_number(adc_output[0]); + usart_out_string("pres: "); + usart_out_number(adc_output[1]); + usart_out_string("temp: "); + usart_out_number(adc_output[2]); + usart_out_string("batt: "); + usart_out_number(adc_output[3]); usart_out_string("drogue: "); usart_out_number(adc_output[4]); usart_out_string(" main: "); -- cgit v1.2.3 From 5577ca3762bfc000b0bc3782c73a8f95996a28a6 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 10:58:57 -0700 Subject: Inc only one on dest addr --- target/adc-serial/adc_serial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/adc-serial/adc_serial.c b/target/adc-serial/adc_serial.c index 349f3d7e..b10d418e 100644 --- a/target/adc-serial/adc_serial.c +++ b/target/adc-serial/adc_serial.c @@ -417,7 +417,7 @@ adc_init(void) DMA_CFG0_TMODE_REPEATED_SINGLE | DMA_CFG0_TRIGGER_ADC_CHALL); dma_config.cfg1 = (DMA_CFG1_SRCINC_0 | - DMA_CFG1_DESTINC_2 | + DMA_CFG1_DESTINC_1 | DMA_CFG1_PRIORITY_NORMAL); dma_config.src_high = ADDRH(&ADCXDATA); -- cgit v1.2.3 From 50cc8e97e76d9b60c622962e1c74cf422dfb2c0f Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 11:01:30 -0700 Subject: Add spacing for serial adc data --- target/adc-serial/adc_serial.c | 10 +++++----- target/adc/adc.c | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'target') diff --git a/target/adc-serial/adc_serial.c b/target/adc-serial/adc_serial.c index b10d418e..b77dd713 100644 --- a/target/adc-serial/adc_serial.c +++ b/target/adc-serial/adc_serial.c @@ -547,15 +547,15 @@ main () adc_run(); usart_out_string("accel: "); usart_out_number(adc_output[0]); - usart_out_string("pres: "); + usart_out_string("\tpres: "); usart_out_number(adc_output[1]); - usart_out_string("temp: "); + usart_out_string("\ttemp: "); usart_out_number(adc_output[2]); - usart_out_string("batt: "); + usart_out_string("\tbatt: "); usart_out_number(adc_output[3]); - usart_out_string("drogue: "); + usart_out_string("\tdrogue: "); usart_out_number(adc_output[4]); - usart_out_string(" main: "); + usart_out_string("\tmain: "); usart_out_number(adc_output[5]); usart_out_string("\r\n"); delay(10); diff --git a/target/adc/adc.c b/target/adc/adc.c index d6d15e6a..bdc6c614 100644 --- a/target/adc/adc.c +++ b/target/adc/adc.c @@ -417,7 +417,7 @@ adc_init(void) DMA_CFG0_TMODE_REPEATED_SINGLE | DMA_CFG0_TRIGGER_ADC_CHALL); dma_config.cfg1 = (DMA_CFG1_SRCINC_0 | - DMA_CFG1_DESTINC_2 | + DMA_CFG1_DESTINC_1 | DMA_CFG1_PRIORITY_NORMAL); dma_config.src_high = ADDRH(&ADCXDATA); -- cgit v1.2.3 From d3732fd405af03c3752a84c4b78da7ef5ebd3744 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 11:14:03 -0700 Subject: Flip ADC bytes around --- target/adc-serial/adc_serial.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) (limited to 'target') diff --git a/target/adc-serial/adc_serial.c b/target/adc-serial/adc_serial.c index b77dd713..fb58b4c2 100644 --- a/target/adc-serial/adc_serial.c +++ b/target/adc-serial/adc_serial.c @@ -405,7 +405,7 @@ struct cc_dma_channel __xdata dma_config; #define ADC_LEN 6 -uint16_t __xdata adc_output[ADC_LEN]; +uint8_t __xdata adc_output[ADC_LEN*2]; #define ADDRH(a) (((uint16_t) (a)) >> 8) #define ADDRL(a) (((uint16_t) (a))) @@ -531,9 +531,13 @@ usart_out_number(uint16_t v) *--num_ptr = '0' + v % 10; v /= 10; } while (v); + while (num_ptr != num_buffer) + *--num_ptr = ' '; usart_out_string(num_ptr); } +#define ADC(n) (((uint16_t) (adc_output[n<<1] << 8)) | (uint16_t) (adc_output[(n<<1)+1])) + main () { P1DIR |= 2; @@ -546,17 +550,17 @@ main () for (;;) { adc_run(); usart_out_string("accel: "); - usart_out_number(adc_output[0]); - usart_out_string("\tpres: "); - usart_out_number(adc_output[1]); - usart_out_string("\ttemp: "); - usart_out_number(adc_output[2]); - usart_out_string("\tbatt: "); - usart_out_number(adc_output[3]); - usart_out_string("\tdrogue: "); - usart_out_number(adc_output[4]); - usart_out_string("\tmain: "); - usart_out_number(adc_output[5]); + usart_out_number(ADC(0)); + usart_out_string("pres: "); + usart_out_number(ADC(1)); + usart_out_string("temp: "); + usart_out_number(ADC(2)); + usart_out_string("batt: "); + usart_out_number(ADC(3)); + usart_out_string("drogue: "); + usart_out_number(ADC(4)); + usart_out_string("main: "); + usart_out_number(ADC(5)); usart_out_string("\r\n"); delay(10); } -- cgit v1.2.3 From 66ee94ed10e3d79b24f45a5c63e58456d4d30343 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 25 Mar 2009 11:37:48 -0700 Subject: Deal with MSB-outputing DMA engine --- target/adc-serial/adc_serial.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) (limited to 'target') diff --git a/target/adc-serial/adc_serial.c b/target/adc-serial/adc_serial.c index fb58b4c2..9f722bb5 100644 --- a/target/adc-serial/adc_serial.c +++ b/target/adc-serial/adc_serial.c @@ -405,7 +405,15 @@ struct cc_dma_channel __xdata dma_config; #define ADC_LEN 6 -uint8_t __xdata adc_output[ADC_LEN*2]; +/* The DMA engine writes to XDATA in MSB order */ +struct dma_xdata16 { + uint8_t high; + uint8_t low; +}; + +struct dma_xdata16 adc_output[ADC_LEN]; + +#define DMA_XDATA16(a,n) ((uint16_t) ((a)[n].high << 8) | (uint16_t) (a[n].low)) #define ADDRH(a) (((uint16_t) (a)) >> 8) #define ADDRL(a) (((uint16_t) (a))) @@ -518,14 +526,16 @@ usart_out_string(uint8_t *string) usart_out_byte(b); } -uint8_t __xdata num_buffer[10]; +#define NUM_LEN 6 + +uint8_t __xdata num_buffer[NUM_LEN]; uint8_t __xdata * __xdata num_ptr; void usart_out_number(uint16_t v) { - num_ptr = num_buffer + 10; + num_ptr = num_buffer + NUM_LEN; *--num_ptr = '\0'; do { *--num_ptr = '0' + v % 10; @@ -533,10 +543,10 @@ usart_out_number(uint16_t v) } while (v); while (num_ptr != num_buffer) *--num_ptr = ' '; - usart_out_string(num_ptr); + usart_out_string(num_buffer); } -#define ADC(n) (((uint16_t) (adc_output[n<<1] << 8)) | (uint16_t) (adc_output[(n<<1)+1])) +#define ADC(n) DMA_XDATA16(adc_output,n) main () { @@ -551,15 +561,15 @@ main () adc_run(); usart_out_string("accel: "); usart_out_number(ADC(0)); - usart_out_string("pres: "); + usart_out_string(" pres: "); usart_out_number(ADC(1)); - usart_out_string("temp: "); + usart_out_string(" temp: "); usart_out_number(ADC(2)); - usart_out_string("batt: "); + usart_out_string(" batt: "); usart_out_number(ADC(3)); - usart_out_string("drogue: "); + usart_out_string(" drogue: "); usart_out_number(ADC(4)); - usart_out_string("main: "); + usart_out_string(" main: "); usart_out_number(ADC(5)); usart_out_string("\r\n"); delay(10); -- cgit v1.2.3 From 5fcfe854d29e1862d9a6adcbef3ef5119eb52fa3 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 1 Apr 2009 00:06:45 -0700 Subject: Add timer-based beep test --- target/adc-serial/adc_serial.c | 3 +- target/beep-timer/Makefile | 47 ++++++++++ target/beep-timer/beep_timer.c | 204 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 253 insertions(+), 1 deletion(-) create mode 100644 target/beep-timer/Makefile create mode 100644 target/beep-timer/beep_timer.c (limited to 'target') diff --git a/target/adc-serial/adc_serial.c b/target/adc-serial/adc_serial.c index 9f722bb5..eba58744 100644 --- a/target/adc-serial/adc_serial.c +++ b/target/adc-serial/adc_serial.c @@ -550,12 +550,13 @@ usart_out_number(uint16_t v) main () { - P1DIR |= 2; + P1DIR = 3; CLKCON = 0; while (!(SLEEP & SLEEP_XOSC_STB)) ; adc_init(); + P1_0 = 1; usart_init(); for (;;) { adc_run(); diff --git a/target/beep-timer/Makefile b/target/beep-timer/Makefile new file mode 100644 index 00000000..008adbd5 --- /dev/null +++ b/target/beep-timer/Makefile @@ -0,0 +1,47 @@ +PROG=beep_timer +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse \ + --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large $(DEBUG) --less-pedantic \ + --no-peep --int-long-reent --float-reent \ + --data-loc 0x30 + +LDFLAGS=--out-fmt-ihx +LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf400 --xram-size 1024 + +LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 + +SRC=$(PROG).c +ADB=$(SRC:.c=.adb) +ASM=$(SRC:.c=.asm) +LNK=$(SRC:.c=.lnk) +LST=$(SRC:.c=.lst) +REL=$(SRC:.c=.rel) +RST=$(SRC:.c=.rst) +SYM=$(SRC:.c=.sym) + +PROGS=$(PROG)-flash.ihx $(PROG)-ram.ihx +PCDB=$(PROGS:.ihx=.cdb) +PLNK=$(PROGS:.ihx=.lnk) +PMAP=$(PROGS:.ihx=.map) +PMEM=$(PROGS:.ihx=.mem) +PAOM=$(PROGS:.ihx=) + +%.rel : %.c + $(CC) -c $(CFLAGS) -o$*.rel $< + +all: $(PROGS) + +$(PROG)-ram.ihx: $(REL) Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o $(PROG)-ram.ihx $(REL) + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o $(PROG)-flash.ihx $(REL) + +$(PROG)-flash.ihx: $(PROG)-ram.ihx + +clean: + rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) + rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) + +install: diff --git a/target/beep-timer/beep_timer.c b/target/beep-timer/beep_timer.c new file mode 100644 index 00000000..53b95495 --- /dev/null +++ b/target/beep-timer/beep_timer.c @@ -0,0 +1,204 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +sfr at 0x80 P0; +sfr at 0x90 P1; +sfr at 0xA0 P2; +sfr at 0xC6 CLKCON; +sfr at 0xbe SLEEP; + +# define SLEEP_USB_EN (1 << 7) +# define SLEEP_XOSC_STB (1 << 6) + +sbit at 0x90 P1_0; +sbit at 0x91 P1_1; +sbit at 0x92 P1_2; +sbit at 0x93 P1_3; +sbit at 0x94 P1_4; +sbit at 0x95 P1_5; +sbit at 0x96 P1_6; +sbit at 0x97 P1_7; + +sfr at 0xF1 PERCFG; +sfr at 0xF2 ADCCFG; +sfr at 0xF3 P0SEL; +sfr at 0xF4 P1SEL; +sfr at 0xF5 P2SEL; + +#define P2SEL_PRI3P1_USART0 (0 << 6) +#define P2SEL_PRI3P1_USART1 (1 << 6) +#define P2SEL_PRI2P1_USART1 (0 << 5) +#define P2SEL_PRI2P1_TIMER3 (1 << 5) +#define P2SEL_PRI1P1_TIMER1 (0 << 4) +#define P2SEL_PRI1P1_TIMER4 (1 << 4) +#define P2SEL_PRI0P1_USART0 (0 << 3) +#define P2SEL_PRI0P1_TIMER1 (1 << 3) +#define P2SEL_SELP2_4_GPIO (0 << 2) +#define P2SEL_SELP2_4_PERIPHERAL (1 << 2) +#define P2SEL_SELP2_3_GPIO (0 << 1) +#define P2SEL_SELP2_3_PERIPHERAL (1 << 1) +#define P2SEL_SELP2_0_GPIO (0 << 0) +#define P2SEL_SELP2_0_PERIPHERAL (1 << 0) + +sfr at 0xFD P0DIR; +sfr at 0xFE P1DIR; +sfr at 0xFF P2DIR; +sfr at 0x8F P0INP; +sfr at 0xF6 P1INP; +sfr at 0xF7 P2INP; + +sfr at 0x89 P0IFG; +sfr at 0x8A P1IFG; +sfr at 0x8B P2IFG; + +sfr at 0xF1 PERCFG; +#define PERCFG_T1CFG_ALT_1 (0 << 6) +#define PERCFG_T1CFG_ALT_2 (1 << 6) + +#define PERCFG_T3CFG_ALT_1 (0 << 5) +#define PERCFG_T3CFG_ALT_2 (1 << 5) + +#define PERCFG_T4CFG_ALT_1 (0 << 4) +#define PERCFG_T4CFG_ALT_2 (1 << 4) + +#define PERCFG_U1CFG_ALT_1 (0 << 1) +#define PERCFG_U1CFG_ALT_2 (1 << 1) + +#define PERCFG_U0CFG_ALT_1 (0 << 0) +#define PERCFG_U0CFG_ALT_2 (1 << 0) + +/* Timer count */ +sfr at 0xCA T3CNT; +sfr at 0xEA T4CNT; + +/* Timer control */ + +sfr at 0xCB T3CTL; +sfr at 0xEB T4CTL; + +#define TxCTL_DIV_1 (0 << 5) +#define TxCTL_DIV_2 (1 << 5) +#define TxCTL_DIV_4 (2 << 5) +#define TxCTL_DIV_8 (3 << 5) +#define TxCTL_DIV_16 (4 << 5) +#define TxCTL_DIV_32 (5 << 5) +#define TxCTL_DIV_64 (6 << 5) +#define TxCTL_DIV_128 (7 << 5) +#define TxCTL_START (1 << 4) +#define TxCTL_OVFIM (1 << 3) +#define TxCTL_CLR (1 << 2) +#define TxCTL_MODE_FREE (0 << 0) +#define TxCTL_MODE_DOWN (1 << 0) +#define TxCTL_MODE_MODULO (2 << 0) +#define TxCTL_MODE_UP_DOWN (3 << 0) + +/* Timer 4 channel 0 compare control */ + +sfr at 0xCC T3CCTL0; +sfr at 0xCE T3CCTL1; +sfr at 0xEC T4CCTL0; +sfr at 0xEE T4CCTL1; + +#define TxCCTLy_IM (1 << 6) +#define TxCCTLy_CMP_SET (0 << 3) +#define TxCCTLy_CMP_CLEAR (1 << 3) +#define TxCCTLy_CMP_TOGGLE (2 << 3) +#define TxCCTLy_CMP_SET_UP_CLEAR_DOWN (3 << 3) +#define TxCCTLy_CMP_CLEAR_UP_SET_DOWN (4 << 3) +#define TxCCTLy_CMP_SET_CLEAR_FF (5 << 3) +#define TxCCTLy_CMP_CLEAR_SET_00 (6 << 3) +#define TxCCTLy_CMP_MODE_ENABLE (1 << 2) + +/* Timer compare value */ +sfr at 0xCD T3CC0; +sfr at 0xCF T3CC1; +sfr at 0xED T4CC0; +sfr at 0xEF T4CC1; + +#define nop() _asm nop _endasm; + +void +delay (unsigned char n) +{ + unsigned char i = 0, j = 0; + + n <<= 1; + while (--n != 0) + while (--j != 0) + while (--i != 0) + nop(); +} + +void +dit() { + T4CTL |= TxCTL_START; + delay(1); + T4CTL &= ~TxCTL_START; + delay(1); +} + +void +dah () { + T4CTL |= TxCTL_START; + delay(3); + T4CTL &= ~TxCTL_START; + delay(1); +} + +void +charspace () { + delay(2); +} + +void +wordspace () { + delay(8); +} + +#define _ dit(); +#define ___ dah(); +#define C charspace(); +#define W wordspace(); + +main () +{ + CLKCON = 0; + while (!(SLEEP & SLEEP_XOSC_STB)) + ; + + /* Use timer 4 alternate config 2 */ + PERCFG = PERCFG_T4CFG_ALT_2; + /* Use P2_4 for timer 4 output */ + P2SEL = P2SEL_SELP2_0_PERIPHERAL; + + T4CCTL0 = TxCCTLy_CMP_TOGGLE|TxCCTLy_CMP_MODE_ENABLE; + T4CC0 = 125; + T4CTL = TxCTL_DIV_32 | TxCTL_MODE_MODULO; + + for (;;) { + ___ _ ___ _ C ___ ___ _ ___ W /* cq */ + ___ _ _ C _ W /* de */ + ___ _ ___ C ___ _ _ C /* kd */ + ___ ___ _ _ _ C _ _ _ C /* 7s */ + ___ ___ _ ___ C ___ ___ _ W /* qg */ + if (T4CC0 == 94) + T4CC0 = 125; + else + T4CC0 = 94; + } +} -- cgit v1.2.3 From 543bedde83cbce5145668e72965e02d892187b59 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 16 Apr 2009 20:38:14 -0700 Subject: Send data --- target/radio/radio.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'target') diff --git a/target/radio/radio.c b/target/radio/radio.c index 90bc47f3..bf893699 100644 --- a/target/radio/radio.c +++ b/target/radio/radio.c @@ -419,7 +419,7 @@ low() { #define DRATE_E 10 #define DRATE_M 163 -#define PACKET_LEN 128 +#define PACKET_LEN 255 /* This are from the table for 433MHz */ @@ -528,19 +528,17 @@ main () /* Set P2_0 to output */ radio_init (); delay(100); - RFST = RFST_SIDLE; - delay(100); - RFST = RFST_STX; - delay(100); - for (;;); -#if 0 + for (;;) { uint8_t i; - for (i = 0; i < PACKET_LEN; i++) { + RFST = RFST_SIDLE; + delay(100); + RFST = RFST_STX; + for (i = 0; i < PACKET_LEN - 1; i++) { while (!RFTXRXIF); RFTXRXIF = 0; RFD = 0x55; } + delay(100); } -#endif } -- cgit v1.2.3 From 04bc51c170c6f22bb5cc16867ce9a307818a7a00 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 17 Apr 2009 10:11:31 -0700 Subject: Add separate xmit/recv programs to radio demo --- target/radio/Makefile | 18 +- target/radio/init.c | 205 +++++++++++++++++++ target/radio/radio.c | 544 -------------------------------------------------- target/radio/radio.h | 428 +++++++++++++++++++++++++++++++++++++++ target/radio/recv.c | 66 ++++++ target/radio/xmit.c | 47 +++++ 6 files changed, 758 insertions(+), 550 deletions(-) create mode 100644 target/radio/init.c delete mode 100644 target/radio/radio.c create mode 100644 target/radio/radio.h create mode 100644 target/radio/recv.c create mode 100644 target/radio/xmit.c (limited to 'target') diff --git a/target/radio/Makefile b/target/radio/Makefile index a26fa458..97706fef 100644 --- a/target/radio/Makefile +++ b/target/radio/Makefile @@ -12,7 +12,7 @@ LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --xram-loc 0xf400 --xram-size 1024 LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --xram-loc 0xf000 --xram-size 1024 -SRC=radio.c +SRC=xmit.c recv.c init.c ADB=$(SRC:.c=.adb) ASM=$(SRC:.c=.asm) LNK=$(SRC:.c=.lnk) @@ -21,7 +21,7 @@ REL=$(SRC:.c=.rel) RST=$(SRC:.c=.rst) SYM=$(SRC:.c=.sym) -PROGS=radio-flash.ihx radio-ram.ihx +PROGS=xmit-flash.ihx xmit-ram.ihx recv-flash.ihx recv-ram.ihx PCDB=$(PROGS:.ihx=.cdb) PLNK=$(PROGS:.ihx=.lnk) PMAP=$(PROGS:.ihx=.map) @@ -33,11 +33,17 @@ PAOM=$(PROGS:.ihx=) all: $(PROGS) -radio-ram.ihx: $(REL) Makefile - $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o radio-ram.ihx $(REL) - $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o radio-flash.ihx $(REL) +xmit-ram.ihx: xmit.rel init.rel Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o xmit-ram.ihx xmit.rel init.rel + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o xmit-flash.ihx xmit.rel init.rel -radio-flash.ihx: radio-ram.ihx +xmit-flash.ihx: xmit-ram.ihx + +recv-ram.ihx: recv.rel init.rel Makefile + $(CC) $(LDFLAGS_RAM) $(CFLAGS) -o recv-ram.ihx recv.rel init.rel + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o recv-flash.ihx recv.rel init.rel + +recv-flash.ihx: recv-ram.ihx clean: rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) diff --git a/target/radio/init.c b/target/radio/init.c new file mode 100644 index 00000000..61efb347 --- /dev/null +++ b/target/radio/init.c @@ -0,0 +1,205 @@ +/* + * Copyright © 2009 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include "radio.h" + +/* Values from SmartRF® Studio for: + * + * Deviation: 20.507812 kHz + * Datarate: 38.360596 kBaud + * Modulation: GFSK + * RF Freq: 434.549927 MHz + * Channel: 99.975586 kHz + * Channel: 0 + * RX filter: 93.75 kHz + */ + +/* + * For 434.550MHz, the frequency value is: + * + * 434.550e6 / (24e6 / 2**16) = 1186611.2 + */ + +#define FREQ_CONTROL 1186611 + +/* + * For IF freq of 140.62kHz, the IF value is: + * + * 140.62e3 / (24e6 / 2**10) = 6 + */ + +#define IF_FREQ_CONTROL 6 + +/* + * For channel bandwidth of 93.75 kHz, the CHANBW_E and CHANBW_M values are + * + * BW = 24e6 / (8 * (4 + M) * 2 ** E) + * + * So, M = 0 and E = 3 + */ + +#define CHANBW_M 0 +#define CHANBW_E 3 + +/* + * For a symbol rate of 38360kBaud, the DRATE_E and DRATE_M values are: + * + * R = (256 + M) * 2** E * 24e6 / 2**28 + * + * So M is 163 and E is 10 + */ + +#define DRATE_E 10 +#define DRATE_M 163 + +/* + * For a channel deviation of 20.5kHz, the DEVIATION_E and DEVIATION_M values are: + * + * F = 24e6/2**17 * (8 + DEVIATION_M) * 2**DEVIATION_E + * + * So M is 6 and E is 3 + */ + +#define DEVIATION_M 6 +#define DEVIATION_E 3 + +#define PACKET_LEN 128 + +/* This are from the table for 433MHz */ + +#define RF_POWER_M30_DBM 0x12 +#define RF_POWER_M20_DBM 0x0e +#define RF_POWER_M15_DBM 0x1d +#define RF_POWER_M10_DBM 0x34 +#define RF_POWER_M5_DBM 0x2c +#define RF_POWER_0_DBM 0x60 +#define RF_POWER_5_DBM 0x84 +#define RF_POWER_7_DBM 0xc8 +#define RF_POWER_10_DBM 0xc0 + +#define RF_POWER RF_POWER_0_DBM + +static __code uint8_t radio_setup[] = { + RF_PA_TABLE7_OFF, RF_POWER, + RF_PA_TABLE6_OFF, RF_POWER, + RF_PA_TABLE5_OFF, RF_POWER, + RF_PA_TABLE4_OFF, RF_POWER, + RF_PA_TABLE3_OFF, RF_POWER, + RF_PA_TABLE2_OFF, RF_POWER, + RF_PA_TABLE1_OFF, RF_POWER, + RF_PA_TABLE0_OFF, RF_POWER, + + RF_FREQ2_OFF, FREQ_CONTROL >> 16, + RF_FREQ1_OFF, FREQ_CONTROL >> 8, + RF_FREQ0_OFF, FREQ_CONTROL >> 0, + + RF_FSCTRL1_OFF, (IF_FREQ_CONTROL << RF_FSCTRL1_FREQ_IF_SHIFT), + RF_FSCTRL0_OFF, (0 << RF_FSCTRL0_FREQOFF_SHIFT), + + RF_MDMCFG4_OFF, ((CHANBW_E << RF_MDMCFG4_CHANBW_E_SHIFT) | + (CHANBW_M << RF_MDMCFG4_CHANBW_M_SHIFT) | + (DRATE_E << RF_MDMCFG4_DRATE_E_SHIFT)), + RF_MDMCFG3_OFF, (DRATE_M << RF_MDMCFG3_DRATE_M_SHIFT), + RF_MDMCFG2_OFF, (RF_MDMCFG2_DEM_DCFILT_OFF | + RF_MDMCFG2_MOD_FORMAT_GFSK | + RF_MDMCFG2_SYNC_MODE_15_16_THRES), + RF_MDMCFG1_OFF, (RF_MDMCFG1_FEC_DIS | + RF_MDMCFG1_NUM_PREAMBLE_4 | + (2 << RF_MDMCFG1_CHANSPC_E_SHIFT)), + RF_MDMCFG0_OFF, (17 << RF_MDMCFG0_CHANSPC_M_SHIFT), + + RF_CHANNR_OFF, 0, + + RF_DEVIATN_OFF, ((DEVIATION_E << RF_DEVIATN_DEVIATION_E_SHIFT) | + (DEVIATION_M << RF_DEVIATN_DEVIATION_M_SHIFT)), + + /* SmartRF says set LODIV_BUF_CURRENT_TX to 0 + * And, we're not using power ramping, so use PA_POWER 0 + */ + RF_FREND0_OFF, ((1 << RF_FREND0_LODIV_BUF_CURRENT_TX_SHIFT) | + (0 << RF_FREND0_PA_POWER_SHIFT)), + + RF_FREND1_OFF, ((1 << RF_FREND1_LNA_CURRENT_SHIFT) | + (1 << RF_FREND1_LNA2MIX_CURRENT_SHIFT) | + (1 << RF_FREND1_LODIV_BUF_CURRENT_RX_SHIFT) | + (2 << RF_FREND1_MIX_CURRENT_SHIFT)), + + RF_FSCAL3_OFF, 0xE9, + RF_FSCAL2_OFF, 0x0A, + RF_FSCAL1_OFF, 0x00, + RF_FSCAL0_OFF, 0x1F, + + RF_TEST2_OFF, 0x88, + RF_TEST1_OFF, 0x31, + RF_TEST0_OFF, 0x09, + + /* default sync values */ + RF_SYNC1_OFF, 0xD3, + RF_SYNC0_OFF, 0x91, + + /* max packet length */ + RF_PKTLEN_OFF, PACKET_LEN, + + RF_PKTCTRL1_OFF, ((1 << PKTCTRL1_PQT_SHIFT)| + PKTCTRL1_APPEND_STATUS| + PKTCTRL1_ADR_CHK_NONE), + RF_PKTCTRL0_OFF, (RF_PKTCTRL0_PKT_FORMAT_NORMAL| + RF_PKTCTRL0_LENGTH_CONFIG_FIXED), + RF_ADDR_OFF, 0x00, + RF_MCSM2_OFF, (RF_MCSM2_RX_TIME_END_OF_PACKET), + RF_MCSM1_OFF, (RF_MCSM1_CCA_MODE_RSSI_BELOW_UNLESS_RECEIVING| + RF_MCSM1_RXOFF_MODE_IDLE| + RF_MCSM1_TXOFF_MODE_IDLE), + RF_MCSM0_OFF, (RF_MCSM0_FS_AUTOCAL_FROM_IDLE| + RF_MCSM0_MAGIC_3| + RF_MCSM0_CLOSE_IN_RX_18DB), + RF_FOCCFG_OFF, (RF_FOCCFG_FOC_PRE_K_3K, + RF_FOCCFG_FOC_POST_K_PRE_K, + RF_FOCCFG_FOC_LIMIT_BW_OVER_4), + RF_BSCFG_OFF, (RF_BSCFG_BS_PRE_K_2K| + RF_BSCFG_BS_PRE_KP_3KP| + RF_BSCFG_BS_POST_KI_PRE_KI| + RF_BSCFG_BS_POST_KP_PRE_KP| + RF_BSCFG_BS_LIMIT_0), + RF_AGCCTRL2_OFF, 0x43, + RF_AGCCTRL1_OFF, 0x40, + RF_AGCCTRL0_OFF, 0x91, + + RF_IOCFG2_OFF, 0x00, + RF_IOCFG1_OFF, 0x00, + RF_IOCFG0_OFF, 0x00, +}; + +void +radio_init(void) { + uint8_t i; + for (i = 0; i < sizeof (radio_setup); i += 2) + RF[radio_setup[i]] = radio_setup[i+1]; +} + +#define nop() _asm nop _endasm; + +void +delay (unsigned char n) +{ + unsigned char i = 0; + + n <<= 1; + while (--n != 0) + while (--i != 0) + nop(); +} diff --git a/target/radio/radio.c b/target/radio/radio.c deleted file mode 100644 index bf893699..00000000 --- a/target/radio/radio.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * Copyright © 2008 Keith Packard - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. - */ - -#include - -sfr at 0x80 P0; -sfr at 0x90 P1; -sfr at 0xA0 P2; -sfr at 0xC6 CLKCON; - -sfr at 0xF1 PERCFG; -sfr at 0xF2 ADCCFG; -sfr at 0xF3 P0SEL; -sfr at 0xF4 P1SEL; -sfr at 0xF5 P2SEL; - -sfr at 0xFD P0DIR; -sfr at 0xFE P1DIR; -sfr at 0xFF P2DIR; -sfr at 0x8F P0INP; -sfr at 0xF6 P1INP; -sfr at 0xF7 P2INP; - -sfr at 0x89 P0IFG; -sfr at 0x8A P1IFG; -sfr at 0x8B P2IFG; - -sfr at 0xD9 RFD; -sfr at 0xE9 RFIF; -sfr at 0xE1 RFST; - -sfr at 0x88 TCON; - -sfr at 0xbe SLEEP; - -# define SLEEP_USB_EN (1 << 7) -# define SLEEP_XOSC_STB (1 << 6) - -sbit at 0x89 RFTXRXIF; - -#define TCON_RFTXRXIF (1 << 1) - -#define RFST_SFSTXON 0x00 -#define RFST_SCAL 0x01 -#define RFST_SRX 0x02 -#define RFST_STX 0x03 -#define RFST_SIDLE 0x04 - -__xdata __at (0xdf00) uint8_t RF[0x3c]; - -__xdata __at (0xdf2f) uint8_t RF_IOCFG2; -#define RF_IOCFG2_OFF 0x2f - -__xdata __at (0xdf30) uint8_t RF_IOCFG1; -#define RF_IOCFG1_OFF 0x30 - -__xdata __at (0xdf31) uint8_t RF_IOCFG0; -#define RF_IOCFG0_OFF 0x31 - -__xdata __at (0xdf00) uint8_t RF_SYNC1; -#define RF_SYNC1_OFF 0x00 - -__xdata __at (0xdf01) uint8_t RF_SYNC0; -#define RF_SYNC0_OFF 0x01 - -__xdata __at (0xdf02) uint8_t RF_PKTLEN; -#define RF_PKTLEN_OFF 0x02 - -__xdata __at (0xdf03) uint8_t RF_PKTCTRL1; -#define RF_PKTCTRL1_OFF 0x03 - -__xdata __at (0xdf04) uint8_t RF_PKTCTRL0; -#define RF_PKTCTRL0_OFF 0x04 - -__xdata __at (0xdf05) uint8_t RF_ADDR; -#define RF_ADDR_OFF 0x05 - -__xdata __at (0xdf06) uint8_t RF_CHANNR; -#define RF_CHANNR_OFF 0x06 - -__xdata __at (0xdf07) uint8_t RF_FSCTRL1; -#define RF_FSCTRL1_OFF 0x07 - -#define RF_FSCTRL1_FREQ_IF_SHIFT (0) - -__xdata __at (0xdf08) uint8_t RF_FSCTRL0; -#define RF_FSCTRL0_OFF 0x08 - -#define RF_FSCTRL0_FREQOFF_SHIFT (0) - -__xdata __at (0xdf09) uint8_t RF_FREQ2; -#define RF_FREQ2_OFF 0x09 - -__xdata __at (0xdf0a) uint8_t RF_FREQ1; -#define RF_FREQ1_OFF 0x0a - -__xdata __at (0xdf0b) uint8_t RF_FREQ0; -#define RF_FREQ0_OFF 0x0b - -__xdata __at (0xdf0c) uint8_t RF_MDMCFG4; -#define RF_MDMCFG4_OFF 0x0c - -#define RF_MDMCFG4_CHANBW_E_SHIFT 6 -#define RF_MDMCFG4_CHANBW_M_SHIFT 4 -#define RF_MDMCFG4_DRATE_E_SHIFT 0 - -__xdata __at (0xdf0d) uint8_t RF_MDMCFG3; -#define RF_MDMCFG3_OFF 0x0d - -#define RF_MDMCFG3_DRATE_M_SHIFT 0 - -__xdata __at (0xdf0e) uint8_t RF_MDMCFG2; -#define RF_MDMCFG2_OFF 0x0e - -#define RF_MDMCFG2_DEM_DCFILT_OFF (1 << 7) - -#define RF_MDMCFG2_MOD_FORMAT_MASK (7 << 4) -#define RF_MDMCFG2_MOD_FORMAT_2_FSK (0 << 4) -#define RF_MDMCFG2_MOD_FORMAT_GFSK (1 << 4) -#define RF_MDMCFG2_MOD_FORMAT_ASK_OOK (3 << 4) -#define RF_MDMCFG2_MOD_FORMAT_MSK (7 << 4) - -#define RF_MDMCFG2_MANCHESTER_EN (1 << 3) - -#define RF_MDMCFG2_SYNC_MODE_MASK (0x7 << 0) -#define RF_MDMCFG2_SYNC_MODE_NONE (0x0 << 0) -#define RF_MDMCFG2_SYNC_MODE_15_16 (0x1 << 0) -#define RF_MDMCFG2_SYNC_MODE_16_16 (0x2 << 0) -#define RF_MDMCFG2_SYNC_MODE_30_32 (0x3 << 0) -#define RF_MDMCFG2_SYNC_MODE_NONE_THRES (0x4 << 0) -#define RF_MDMCFG2_SYNC_MODE_15_16_THRES (0x5 << 0) -#define RF_MDMCFG2_SYNC_MODE_16_16_THRES (0x6 << 0) -#define RF_MDMCFG2_SYNC_MODE_30_32_THRES (0x7 << 0) - -__xdata __at (0xdf0f) uint8_t RF_MDMCFG1; -#define RF_MDMCFG1_OFF 0x0f - -#define RF_MDMCFG1_FEC_EN (1 << 7) - -#define RF_MDMCFG1_NUM_PREAMBLE_MASK (7 << 4) -#define RF_MDMCFG1_NUM_PREAMBLE_2 (0 << 4) -#define RF_MDMCFG1_NUM_PREAMBLE_3 (1 << 4) -#define RF_MDMCFG1_NUM_PREAMBLE_4 (2 << 4) -#define RF_MDMCFG1_NUM_PREAMBLE_6 (3 << 4) -#define RF_MDMCFG1_NUM_PREAMBLE_8 (4 << 4) -#define RF_MDMCFG1_NUM_PREAMBLE_12 (5 << 4) -#define RF_MDMCFG1_NUM_PREAMBLE_16 (6 << 4) -#define RF_MDMCFG1_NUM_PREAMBLE_24 (7 << 4) - -#define RF_MDMCFG1_CHANSPC_E_MASK (3 << 0) -#define RF_MDMCFG1_CHANSPC_E_SHIFT (0) - -__xdata __at (0xdf10) uint8_t RF_MDMCFG0; -#define RF_MDMCFG0_OFF 0x10 - -#define RF_MDMCFG0_CHANSPC_M_SHIFT (0) - -__xdata __at (0xdf11) uint8_t RF_DEVIATN; -#define RF_DEVIATN_OFF 0x11 - -#define RF_DEVIATN_DEVIATION_E_SHIFT 4 -#define RF_DEVIATN_DEVIATION_M_SHIFT 0 - -__xdata __at (0xdf12) uint8_t RF_MCSM2; -#define RF_MCSM2_OFF 0x12 - -__xdata __at (0xdf13) uint8_t RF_MCSM1; -#define RF_MCSM1_OFF 0x13 - -__xdata __at (0xdf14) uint8_t RF_MCSM0; -#define RF_MCSM0_OFF 0x14 - -__xdata __at (0xdf15) uint8_t RF_FOCCFG; -#define RF_FOCCFG_OFF 0x15 - -__xdata __at (0xdf16) uint8_t RF_BSCFG; -#define RF_BSCFG_OFF 0x16 - -__xdata __at (0xdf17) uint8_t RF_AGCCTRL2; -#define RF_AGCCTRL2_OFF 0x17 - -__xdata __at (0xdf18) uint8_t RF_AGCCTRL1; -#define RF_AGCCTRL1_OFF 0x18 - -__xdata __at (0xdf19) uint8_t RF_AGCCTRL0; -#define RF_AGCCTRL0_OFF 0x19 - -__xdata __at (0xdf1a) uint8_t RF_FREND1; -#define RF_FREND1_OFF 0x1a - -#define RF_FREND1_LNA_CURRENT_SHIFT 6 -#define RF_FREND1_LNA2MIX_CURRENT_SHIFT 4 -#define RF_FREND1_LODIV_BUF_CURRENT_RX_SHIFT 2 -#define RF_FREND1_MIX_CURRENT_SHIFT 0 - -__xdata __at (0xdf1b) uint8_t RF_FREND0; -#define RF_FREND0_OFF 0x1b - -#define RF_FREND0_LODIV_BUF_CURRENT_TX_MASK (0x3 << 4) -#define RF_FREND0_LODIV_BUF_CURRENT_TX_SHIFT 4 -#define RF_FREND0_PA_POWER_MASK (0x7) -#define RF_FREND0_PA_POWER_SHIFT 0 - -__xdata __at (0xdf1c) uint8_t RF_FSCAL3; -#define RF_FSCAL3_OFF 0x1c - -__xdata __at (0xdf1d) uint8_t RF_FSCAL2; -#define RF_FSCAL2_OFF 0x1d - -__xdata __at (0xdf1e) uint8_t RF_FSCAL1; -#define RF_FSCAL1_OFF 0x1e - -__xdata __at (0xdf1f) uint8_t RF_FSCAL0; -#define RF_FSCAL0_OFF 0x1f - -__xdata __at (0xdf23) uint8_t RF_TEST2; -#define RF_TEST2_OFF 0x23 - -#define RF_TEST2_NORMAL_MAGIC 0x88 -#define RF_TEST2_RX_LOW_DATA_RATE_MAGIC 0x81 - -__xdata __at (0xdf24) uint8_t RF_TEST1; -#define RF_TEST1_OFF 0x24 - -#define RF_TEST1_TX_MAGIC 0x31 -#define RF_TEST1_RX_LOW_DATA_RATE_MAGIC 0x35 - -__xdata __at (0xdf25) uint8_t RF_TEST0; -#define RF_TEST0_OFF 0x25 - -#define RF_TEST0_7_2_MASK (0xfc) -#define RF_TEST0_VCO_SEL_CAL_EN (1 << 1) -#define RF_TEST0_0_MASK (1) - -/* These are undocumented, and must be computed - * using the provided tool. - */ -__xdata __at (0xdf27) uint8_t RF_PA_TABLE7; -#define RF_PA_TABLE7_OFF 0x27 - -__xdata __at (0xdf28) uint8_t RF_PA_TABLE6; -#define RF_PA_TABLE6_OFF 0x28 - -__xdata __at (0xdf29) uint8_t RF_PA_TABLE5; -#define RF_PA_TABLE5_OFF 0x29 - -__xdata __at (0xdf2a) uint8_t RF_PA_TABLE4; -#define RF_PA_TABLE4_OFF 0x2a - -__xdata __at (0xdf2b) uint8_t RF_PA_TABLE3; -#define RF_PA_TABLE3_OFF 0x2b - -__xdata __at (0xdf2c) uint8_t RF_PA_TABLE2; -#define RF_PA_TABLE2_OFF 0x2c - -__xdata __at (0xdf2d) uint8_t RF_PA_TABLE1; -#define RF_PA_TABLE1_OFF 0x2d - -__xdata __at (0xdf2e) uint8_t RF_PA_TABLE0; -#define RF_PA_TABLE0_OFF 0x2e - -__xdata __at (0xdf36) uint8_t RF_PARTNUM; -#define RF_PARTNUM_OFF 0x36 - -__xdata __at (0xdf37) uint8_t RF_VERSION; -#define RF_VERSION_OFF 0x37 - -__xdata __at (0xdf38) uint8_t RF_FREQEST; -#define RF_FREQEST_OFF 0x38 - -__xdata __at (0xdf39) uint8_t RF_LQI; -#define RF_LQI_OFF 0x39 - -#define RF_LQI_CRC_OK (1 << 7) -#define RF_LQI_LQI_EST_MASK (0x7f) - -__xdata __at (0xdf3a) uint8_t RF_RSSI; -#define RF_RSSI_OFF 0x3a - -__xdata __at (0xdf3b) uint8_t RF_MARCSTATE; -#define RF_MARCSTATE_OFF 0x3b - -#define RF_MARCSTATE_MASK 0x0f -#define RF_MARCSTATE_SLEEP 0x00 -#define RF_MARCSTATE_IDLE 0x01 -#define RF_MARCSTATE_VCOON_MC 0x03 -#define RF_MARCSTATE_REGON_MC 0x04 -#define RF_MARCSTATE_MANCAL 0x05 -#define RF_MARCSTATE_VCOON 0x06 -#define RF_MARCSTATE_REGON 0x07 -#define RF_MARCSTATE_STARTCAL 0x08 -#define RF_MARCSTATE_BWBOOST 0x09 -#define RF_MARCSTATE_FS_LOCK 0x0a -#define RF_MARCSTATE_IFADCON 0x0b -#define RF_MARCSTATE_ENDCAL 0x0c -#define RF_MARCSTATE_RX 0x0d -#define RF_MARCSTATE_RX_END 0x0e -#define RF_MARCSTATE_RX_RST 0x0f -#define RF_MARCSTATE_TXRX_SWITCH 0x10 -#define RF_MARCSTATE_RX_OVERFLOW 0x11 -#define RF_MARCSTATE_FSTXON 0x12 -#define RF_MARCSTATE_TX 0x13 -#define RF_MARCSTATE_TX_END 0x14 -#define RF_MARCSTATE_RXTX_SWITCH 0x15 -#define RF_MARCSTATE_TX_UNDERFLOW 0x16 - - -__xdata __at (0xdf3c) uint8_t RF_PKTSTATUS; -#define RF_PKTSTATUS_OFF 0x3c - -#define RF_PKTSTATUS_CRC_OK (1 << 7) -#define RF_PKTSTATUS_CS (1 << 6) -#define RF_PKTSTATUS_PQT_REACHED (1 << 5) -#define RF_PKTSTATUS_CCA (1 << 4) -#define RF_PKTSTATUS_SFD (1 << 3) - -__xdata __at (0xdf3d) uint8_t RF_VCO_VC_DAC; -#define RF_VCO_VC_DAC_OFF 0x3d - -#define nop() _asm nop _endasm; - -void -delay (unsigned char n) -{ - unsigned char i = 0; - - n <<= 1; - while (--n != 0) - while (--i != 0) - nop(); -} - -void -tone (unsigned char n, unsigned char m) -{ - unsigned char i = 0; - while (--m != 0) { - i = 128; - while (--i != 0) { - P2 = 0xff; - delay(n); - P2 = 0xfe; - delay(n); - } - } -} - -void -high() { - tone(1, 2); -} - -void -low() { - tone(2, 1); -} - -/* Values from SmartRF® Studio for: - * - * Deviation: 20.507812 kHz - * Datarate: 38.360596 kBaud - * Modulation: GFSK - * RF Freq: 434.549927 MHz - * Channel: 99.975586 kHz - * Channel: 0 - * RX filter: 93.75 kHz - */ - -/* - * For 434.550MHz, the frequency value is: - * - * 434.550e6 / (24e6 / 2**16) = 1186611.2 - */ - -#define FREQ_CONTROL 1186611 - -/* - * For IF freq of 140.62kHz, the IF value is: - * - * 140.62e3 / (24e6 / 2**10) = 6 - */ - -#define IF_FREQ_CONTROL 6 - -/* - * For channel bandwidth of 93.75 kHz, the CHANBW_E and CHANBW_M values are - * - * BW = 24e6 / (8 * (4 + M) * 2 ** E) - * - * So, M = 0 and E = 3 - */ - -#define CHANBW_M 0 -#define CHANBW_E 3 - -/* - * For a symbol rate of 38360kBaud, the DRATE_E and DRATE_M values are: - * - * R = (256 + M) * 2** E * 24e6 / 2**28 - * - * So M is 163 and E is 10 - */ - -#define DRATE_E 10 -#define DRATE_M 163 - -#define PACKET_LEN 255 - -/* This are from the table for 433MHz */ - -#define RF_POWER_M30_DBM 0x12 -#define RF_POWER_M20_DBM 0x0e -#define RF_POWER_M15_DBM 0x1d -#define RF_POWER_M10_DBM 0x34 -#define RF_POWER_M5_DBM 0x2c -#define RF_POWER_0_DBM 0x60 -#define RF_POWER_5_DBM 0x84 -#define RF_POWER_7_DBM 0xc8 -#define RF_POWER_10_DBM 0xc0 - -#define RF_POWER RF_POWER_0_DBM - -static __code uint8_t radio_setup[] = { - RF_PA_TABLE7_OFF, RF_POWER, - RF_PA_TABLE6_OFF, RF_POWER, - RF_PA_TABLE5_OFF, RF_POWER, - RF_PA_TABLE4_OFF, RF_POWER, - RF_PA_TABLE3_OFF, RF_POWER, - RF_PA_TABLE2_OFF, RF_POWER, - RF_PA_TABLE1_OFF, RF_POWER, - RF_PA_TABLE0_OFF, RF_POWER, - - RF_FREQ2_OFF, FREQ_CONTROL >> 16, - RF_FREQ1_OFF, FREQ_CONTROL >> 8, - RF_FREQ0_OFF, FREQ_CONTROL >> 0, - - RF_FSCTRL1_OFF, (IF_FREQ_CONTROL << RF_FSCTRL1_FREQ_IF_SHIFT), - RF_FSCTRL0_OFF, (0 << RF_FSCTRL0_FREQOFF_SHIFT), - - RF_MDMCFG4_OFF, ((CHANBW_E << RF_MDMCFG4_CHANBW_E_SHIFT) | - (CHANBW_M << RF_MDMCFG4_CHANBW_M_SHIFT) | - (DRATE_E << RF_MDMCFG4_DRATE_E_SHIFT)), - RF_MDMCFG3_OFF, (DRATE_M << RF_MDMCFG3_DRATE_M_SHIFT), - RF_MDMCFG2_OFF, (RF_MDMCFG2_DEM_DCFILT_OFF | - RF_MDMCFG2_MOD_FORMAT_GFSK | - RF_MDMCFG2_SYNC_MODE_NONE), - RF_MDMCFG1_OFF, (RF_MDMCFG1_NUM_PREAMBLE_4 | - (2 << RF_MDMCFG1_CHANSPC_E_SHIFT)), - RF_MDMCFG0_OFF, (17 << RF_MDMCFG0_CHANSPC_M_SHIFT), - - RF_CHANNR_OFF, 0, - - RF_DEVIATN_OFF, ((3 << RF_DEVIATN_DEVIATION_E_SHIFT) | - (6 << RF_DEVIATN_DEVIATION_M_SHIFT)), - - /* SmartRF says set LODIV_BUF_CURRENT_TX to 0 - * And, we're not using power ramping, so use PA_POWER 0 - */ - RF_FREND0_OFF, ((1 << RF_FREND0_LODIV_BUF_CURRENT_TX_SHIFT) | - (0 << RF_FREND0_PA_POWER_SHIFT)), - - RF_FREND1_OFF, ((1 << RF_FREND1_LNA_CURRENT_SHIFT) | - (1 << RF_FREND1_LNA2MIX_CURRENT_SHIFT) | - (1 << RF_FREND1_LODIV_BUF_CURRENT_RX_SHIFT) | - (2 << RF_FREND1_MIX_CURRENT_SHIFT)), - RF_MCSM0_OFF, 0x18, - RF_FOCCFG_OFF, 0x16, - RF_BSCFG_OFF, 0x6C, - - RF_AGCCTRL2_OFF, 0x43, - RF_AGCCTRL1_OFF, 0x40, - RF_AGCCTRL0_OFF, 0x91, - - RF_FSCAL3_OFF, 0xE9, - RF_FSCAL2_OFF, 0x0A, - RF_FSCAL1_OFF, 0x00, - RF_FSCAL0_OFF, 0x1F, - - RF_TEST2_OFF, 0x88, - RF_TEST1_OFF, 0x31, - RF_TEST0_OFF, 0x09, - - /* default sync values */ - RF_SYNC1_OFF, 0xD3, - RF_SYNC0_OFF, 0x91, - - /* max packet length */ - RF_PKTLEN_OFF, PACKET_LEN, - - RF_PKTCTRL1_OFF, 0x04, - RF_PKTCTRL0_OFF, 0x00, - RF_ADDR_OFF, 0x00, - RF_MCSM2_OFF, 0x07, - RF_MCSM1_OFF, 0x30, - - RF_IOCFG2_OFF, 0x00, - RF_IOCFG1_OFF, 0x00, - RF_IOCFG0_OFF, 0x00, -}; - -void -radio_init() { - uint8_t i; - for (i = 0; i < sizeof (radio_setup); i += 2) - RF[radio_setup[i]] = radio_setup[i+1]; -} - -main () -{ - CLKCON = 0; - while (!(SLEEP & SLEEP_XOSC_STB)) - ; - /* Set P2_0 to output */ - radio_init (); - delay(100); - - for (;;) { - uint8_t i; - RFST = RFST_SIDLE; - delay(100); - RFST = RFST_STX; - for (i = 0; i < PACKET_LEN - 1; i++) { - while (!RFTXRXIF); - RFTXRXIF = 0; - RFD = 0x55; - } - delay(100); - } -} diff --git a/target/radio/radio.h b/target/radio/radio.h new file mode 100644 index 00000000..d501ad12 --- /dev/null +++ b/target/radio/radio.h @@ -0,0 +1,428 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include + +sfr at 0x80 P0; +sfr at 0x90 P1; +sbit at 0x90 P1_0; +sbit at 0x91 P1_1; +sbit at 0x92 P1_2; +sbit at 0x93 P1_3; +sbit at 0x94 P1_4; +sbit at 0x95 P1_5; +sbit at 0x96 P1_6; +sbit at 0x97 P1_7; + +sfr at 0xA0 P2; +sfr at 0xC6 CLKCON; + +sfr at 0xF1 PERCFG; +sfr at 0xF2 ADCCFG; +sfr at 0xF3 P0SEL; +sfr at 0xF4 P1SEL; +sfr at 0xF5 P2SEL; + +sfr at 0xFD P0DIR; +sfr at 0xFE P1DIR; +sfr at 0xFF P2DIR; +sfr at 0x8F P0INP; +sfr at 0xF6 P1INP; +sfr at 0xF7 P2INP; + +sfr at 0x89 P0IFG; +sfr at 0x8A P1IFG; +sfr at 0x8B P2IFG; + +sfr at 0xD9 RFD; +sfr at 0xE9 RFIF; +#define RFIF_IM_TXUNF (1 << 7) +#define RFIF_IM_RXOVF (1 << 6) +#define RFIF_IM_TIMEOUT (1 << 5) +#define RFIF_IM_DONE (1 << 4) +#define RFIF_IM_CS (1 << 3) +#define RFIF_IM_PQT (1 << 2) +#define RFIF_IM_CCA (1 << 1) +#define RFIF_IM_SFD (1 << 0) + +sfr at 0xE1 RFST; + +sfr at 0x88 TCON; + +sfr at 0xbe SLEEP; + +# define SLEEP_USB_EN (1 << 7) +# define SLEEP_XOSC_STB (1 << 6) + +sbit at 0x89 RFTXRXIF; + +#define TCON_RFTXRXIF (1 << 1) + +#define RFST_SFSTXON 0x00 +#define RFST_SCAL 0x01 +#define RFST_SRX 0x02 +#define RFST_STX 0x03 +#define RFST_SIDLE 0x04 + +__xdata __at (0xdf00) uint8_t RF[0x3c]; + +__xdata __at (0xdf2f) uint8_t RF_IOCFG2; +#define RF_IOCFG2_OFF 0x2f + +__xdata __at (0xdf30) uint8_t RF_IOCFG1; +#define RF_IOCFG1_OFF 0x30 + +__xdata __at (0xdf31) uint8_t RF_IOCFG0; +#define RF_IOCFG0_OFF 0x31 + +__xdata __at (0xdf00) uint8_t RF_SYNC1; +#define RF_SYNC1_OFF 0x00 + +__xdata __at (0xdf01) uint8_t RF_SYNC0; +#define RF_SYNC0_OFF 0x01 + +__xdata __at (0xdf02) uint8_t RF_PKTLEN; +#define RF_PKTLEN_OFF 0x02 + +__xdata __at (0xdf03) uint8_t RF_PKTCTRL1; +#define RF_PKTCTRL1_OFF 0x03 +#define PKTCTRL1_PQT_MASK (0x7 << 5) +#define PKTCTRL1_PQT_SHIFT 5 +#define PKTCTRL1_APPEND_STATUS (1 << 2) +#define PKTCTRL1_ADR_CHK_NONE (0 << 0) +#define PKTCTRL1_ADR_CHK_NO_BROADCAST (1 << 0) +#define PKTCTRL1_ADR_CHK_00_BROADCAST (2 << 0) +#define PKTCTRL1_ADR_CHK_00_FF_BROADCAST (3 << 0) + +__xdata __at (0xdf04) uint8_t RF_PKTCTRL0; +#define RF_PKTCTRL0_OFF 0x04 +#define RF_PKTCTRL0_WHITE_DATA (1 << 6) +#define RF_PKTCTRL0_PKT_FORMAT_NORMAL (0 << 4) +#define RF_PKTCTRL0_PKT_FORMAT_RANDOM (2 << 4) +#define RF_PKTCTRL0_CRC_EN (1 << 2) +#define RF_PKTCTRL0_LENGTH_CONFIG_FIXED (0 << 0) +#define RF_PKTCTRL0_LENGTH_CONFIG_VARIABLE (1 << 0) + +__xdata __at (0xdf05) uint8_t RF_ADDR; +#define RF_ADDR_OFF 0x05 + +__xdata __at (0xdf06) uint8_t RF_CHANNR; +#define RF_CHANNR_OFF 0x06 + +__xdata __at (0xdf07) uint8_t RF_FSCTRL1; +#define RF_FSCTRL1_OFF 0x07 + +#define RF_FSCTRL1_FREQ_IF_SHIFT (0) + +__xdata __at (0xdf08) uint8_t RF_FSCTRL0; +#define RF_FSCTRL0_OFF 0x08 + +#define RF_FSCTRL0_FREQOFF_SHIFT (0) + +__xdata __at (0xdf09) uint8_t RF_FREQ2; +#define RF_FREQ2_OFF 0x09 + +__xdata __at (0xdf0a) uint8_t RF_FREQ1; +#define RF_FREQ1_OFF 0x0a + +__xdata __at (0xdf0b) uint8_t RF_FREQ0; +#define RF_FREQ0_OFF 0x0b + +__xdata __at (0xdf0c) uint8_t RF_MDMCFG4; +#define RF_MDMCFG4_OFF 0x0c + +#define RF_MDMCFG4_CHANBW_E_SHIFT 6 +#define RF_MDMCFG4_CHANBW_M_SHIFT 4 +#define RF_MDMCFG4_DRATE_E_SHIFT 0 + +__xdata __at (0xdf0d) uint8_t RF_MDMCFG3; +#define RF_MDMCFG3_OFF 0x0d + +#define RF_MDMCFG3_DRATE_M_SHIFT 0 + +__xdata __at (0xdf0e) uint8_t RF_MDMCFG2; +#define RF_MDMCFG2_OFF 0x0e + +#define RF_MDMCFG2_DEM_DCFILT_OFF (1 << 7) +#define RF_MDMCFG2_DEM_DCFILT_ON (0 << 7) + +#define RF_MDMCFG2_MOD_FORMAT_MASK (7 << 4) +#define RF_MDMCFG2_MOD_FORMAT_2_FSK (0 << 4) +#define RF_MDMCFG2_MOD_FORMAT_GFSK (1 << 4) +#define RF_MDMCFG2_MOD_FORMAT_ASK_OOK (3 << 4) +#define RF_MDMCFG2_MOD_FORMAT_MSK (7 << 4) + +#define RF_MDMCFG2_MANCHESTER_EN (1 << 3) + +#define RF_MDMCFG2_SYNC_MODE_MASK (0x7 << 0) +#define RF_MDMCFG2_SYNC_MODE_NONE (0x0 << 0) +#define RF_MDMCFG2_SYNC_MODE_15_16 (0x1 << 0) +#define RF_MDMCFG2_SYNC_MODE_16_16 (0x2 << 0) +#define RF_MDMCFG2_SYNC_MODE_30_32 (0x3 << 0) +#define RF_MDMCFG2_SYNC_MODE_NONE_THRES (0x4 << 0) +#define RF_MDMCFG2_SYNC_MODE_15_16_THRES (0x5 << 0) +#define RF_MDMCFG2_SYNC_MODE_16_16_THRES (0x6 << 0) +#define RF_MDMCFG2_SYNC_MODE_30_32_THRES (0x7 << 0) + +__xdata __at (0xdf0f) uint8_t RF_MDMCFG1; +#define RF_MDMCFG1_OFF 0x0f + +#define RF_MDMCFG1_FEC_EN (1 << 7) +#define RF_MDMCFG1_FEC_DIS (0 << 7) + +#define RF_MDMCFG1_NUM_PREAMBLE_MASK (7 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_2 (0 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_3 (1 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_4 (2 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_6 (3 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_8 (4 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_12 (5 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_16 (6 << 4) +#define RF_MDMCFG1_NUM_PREAMBLE_24 (7 << 4) + +#define RF_MDMCFG1_CHANSPC_E_MASK (3 << 0) +#define RF_MDMCFG1_CHANSPC_E_SHIFT (0) + +__xdata __at (0xdf10) uint8_t RF_MDMCFG0; +#define RF_MDMCFG0_OFF 0x10 + +#define RF_MDMCFG0_CHANSPC_M_SHIFT (0) + +__xdata __at (0xdf11) uint8_t RF_DEVIATN; +#define RF_DEVIATN_OFF 0x11 + +#define RF_DEVIATN_DEVIATION_E_SHIFT 4 +#define RF_DEVIATN_DEVIATION_M_SHIFT 0 + +__xdata __at (0xdf12) uint8_t RF_MCSM2; +#define RF_MCSM2_OFF 0x12 +#define RF_MCSM2_RX_TIME_RSSI (1 << 4) +#define RF_MCSM2_RX_TIME_QUAL (1 << 3) +#define RF_MCSM2_RX_TIME_MASK (0x7) +#define RF_MCSM2_RX_TIME_SHIFT 0 +#define RF_MCSM2_RX_TIME_END_OF_PACKET (7) + +__xdata __at (0xdf13) uint8_t RF_MCSM1; +#define RF_MCSM1_OFF 0x13 +#define RF_MCSM1_CCA_MODE_ALWAYS (0 << 4) +#define RF_MCSM1_CCA_MODE_RSSI_BELOW (1 << 4) +#define RF_MCSM1_CCA_MODE_UNLESS_RECEIVING (2 << 4) +#define RF_MCSM1_CCA_MODE_RSSI_BELOW_UNLESS_RECEIVING (3 << 4) +#define RF_MCSM1_RXOFF_MODE_IDLE (0 << 2) +#define RF_MCSM1_RXOFF_MODE_FSTXON (1 << 2) +#define RF_MCSM1_RXOFF_MODE_TX (2 << 2) +#define RF_MCSM1_RXOFF_MODE_RX (3 << 2) +#define RF_MCSM1_TXOFF_MODE_IDLE (0 << 0) +#define RF_MCSM1_TXOFF_MODE_FSTXON (1 << 0) +#define RF_MCSM1_TXOFF_MODE_TX (2 << 0) +#define RF_MCSM1_TXOFF_MODE_RX (3 << 0) + +__xdata __at (0xdf14) uint8_t RF_MCSM0; +#define RF_MCSM0_OFF 0x14 +#define RF_MCSM0_FS_AUTOCAL_NEVER (0 << 4) +#define RF_MCSM0_FS_AUTOCAL_FROM_IDLE (1 << 4) +#define RF_MCSM0_FS_AUTOCAL_TO_IDLE (2 << 4) +#define RF_MCSM0_FS_AUTOCAL_TO_IDLE_EVERY_4 (3 << 4) +#define RF_MCSM0_MAGIC_3 (1 << 3) +#define RF_MCSM0_MAGIC_2 (1 << 2) +#define RF_MCSM0_CLOSE_IN_RX_0DB (0 << 0) +#define RF_MCSM0_CLOSE_IN_RX_6DB (1 << 0) +#define RF_MCSM0_CLOSE_IN_RX_12DB (2 << 0) +#define RF_MCSM0_CLOSE_IN_RX_18DB (3 << 0) + +__xdata __at (0xdf15) uint8_t RF_FOCCFG; +#define RF_FOCCFG_OFF 0x15 +#define RF_FOCCFG_FOC_BS_CS_GATE (1 << 5) +#define RF_FOCCFG_FOC_PRE_K_1K (0 << 3) +#define RF_FOCCFG_FOC_PRE_K_2K (1 << 3) +#define RF_FOCCFG_FOC_PRE_K_3K (2 << 3) +#define RF_FOCCFG_FOC_PRE_K_4K (3 << 3) +#define RF_FOCCFG_FOC_POST_K_PRE_K (0 << 2) +#define RF_FOCCFG_FOC_POST_K_PRE_K_OVER_2 (1 << 2) +#define RF_FOCCFG_FOC_LIMIT_0 (0 << 0) +#define RF_FOCCFG_FOC_LIMIT_BW_OVER_8 (1 << 0) +#define RF_FOCCFG_FOC_LIMIT_BW_OVER_4 (2 << 0) +#define RF_FOCCFG_FOC_LIMIT_BW_OVER_2 (3 << 0) + +__xdata __at (0xdf16) uint8_t RF_BSCFG; +#define RF_BSCFG_OFF 0x16 +#define RF_BSCFG_BS_PRE_K_1K (0 << 6) +#define RF_BSCFG_BS_PRE_K_2K (1 << 6) +#define RF_BSCFG_BS_PRE_K_3K (2 << 6) +#define RF_BSCFG_BS_PRE_K_4K (3 << 6) +#define RF_BSCFG_BS_PRE_KP_1KP (0 << 4) +#define RF_BSCFG_BS_PRE_KP_2KP (1 << 4) +#define RF_BSCFG_BS_PRE_KP_3KP (2 << 4) +#define RF_BSCFG_BS_PRE_KP_4KP (3 << 4) +#define RF_BSCFG_BS_POST_KI_PRE_KI (0 << 3) +#define RF_BSCFG_BS_POST_KI_PRE_KI_OVER_2 (1 << 3) +#define RF_BSCFG_BS_POST_KP_PRE_KP (0 << 2) +#define RF_BSCFG_BS_POST_KP_PRE_KP_OVER_2 (1 << 2) +#define RF_BSCFG_BS_LIMIT_0 (0 << 0) +#define RF_BSCFG_BS_LIMIT_3_125 (1 << 0) +#define RF_BSCFG_BS_LIMIT_6_25 (2 << 0) +#define RF_BSCFG_BS_LIMIT_12_5 (3 << 0) + +__xdata __at (0xdf17) uint8_t RF_AGCCTRL2; +#define RF_AGCCTRL2_OFF 0x17 + +__xdata __at (0xdf18) uint8_t RF_AGCCTRL1; +#define RF_AGCCTRL1_OFF 0x18 + +__xdata __at (0xdf19) uint8_t RF_AGCCTRL0; +#define RF_AGCCTRL0_OFF 0x19 + +__xdata __at (0xdf1a) uint8_t RF_FREND1; +#define RF_FREND1_OFF 0x1a + +#define RF_FREND1_LNA_CURRENT_SHIFT 6 +#define RF_FREND1_LNA2MIX_CURRENT_SHIFT 4 +#define RF_FREND1_LODIV_BUF_CURRENT_RX_SHIFT 2 +#define RF_FREND1_MIX_CURRENT_SHIFT 0 + +__xdata __at (0xdf1b) uint8_t RF_FREND0; +#define RF_FREND0_OFF 0x1b + +#define RF_FREND0_LODIV_BUF_CURRENT_TX_MASK (0x3 << 4) +#define RF_FREND0_LODIV_BUF_CURRENT_TX_SHIFT 4 +#define RF_FREND0_PA_POWER_MASK (0x7) +#define RF_FREND0_PA_POWER_SHIFT 0 + +__xdata __at (0xdf1c) uint8_t RF_FSCAL3; +#define RF_FSCAL3_OFF 0x1c + +__xdata __at (0xdf1d) uint8_t RF_FSCAL2; +#define RF_FSCAL2_OFF 0x1d + +__xdata __at (0xdf1e) uint8_t RF_FSCAL1; +#define RF_FSCAL1_OFF 0x1e + +__xdata __at (0xdf1f) uint8_t RF_FSCAL0; +#define RF_FSCAL0_OFF 0x1f + +__xdata __at (0xdf23) uint8_t RF_TEST2; +#define RF_TEST2_OFF 0x23 + +#define RF_TEST2_NORMAL_MAGIC 0x88 +#define RF_TEST2_RX_LOW_DATA_RATE_MAGIC 0x81 + +__xdata __at (0xdf24) uint8_t RF_TEST1; +#define RF_TEST1_OFF 0x24 + +#define RF_TEST1_TX_MAGIC 0x31 +#define RF_TEST1_RX_LOW_DATA_RATE_MAGIC 0x35 + +__xdata __at (0xdf25) uint8_t RF_TEST0; +#define RF_TEST0_OFF 0x25 + +#define RF_TEST0_7_2_MASK (0xfc) +#define RF_TEST0_VCO_SEL_CAL_EN (1 << 1) +#define RF_TEST0_0_MASK (1) + +/* These are undocumented, and must be computed + * using the provided tool. + */ +__xdata __at (0xdf27) uint8_t RF_PA_TABLE7; +#define RF_PA_TABLE7_OFF 0x27 + +__xdata __at (0xdf28) uint8_t RF_PA_TABLE6; +#define RF_PA_TABLE6_OFF 0x28 + +__xdata __at (0xdf29) uint8_t RF_PA_TABLE5; +#define RF_PA_TABLE5_OFF 0x29 + +__xdata __at (0xdf2a) uint8_t RF_PA_TABLE4; +#define RF_PA_TABLE4_OFF 0x2a + +__xdata __at (0xdf2b) uint8_t RF_PA_TABLE3; +#define RF_PA_TABLE3_OFF 0x2b + +__xdata __at (0xdf2c) uint8_t RF_PA_TABLE2; +#define RF_PA_TABLE2_OFF 0x2c + +__xdata __at (0xdf2d) uint8_t RF_PA_TABLE1; +#define RF_PA_TABLE1_OFF 0x2d + +__xdata __at (0xdf2e) uint8_t RF_PA_TABLE0; +#define RF_PA_TABLE0_OFF 0x2e + +__xdata __at (0xdf36) uint8_t RF_PARTNUM; +#define RF_PARTNUM_OFF 0x36 + +__xdata __at (0xdf37) uint8_t RF_VERSION; +#define RF_VERSION_OFF 0x37 + +__xdata __at (0xdf38) uint8_t RF_FREQEST; +#define RF_FREQEST_OFF 0x38 + +__xdata __at (0xdf39) uint8_t RF_LQI; +#define RF_LQI_OFF 0x39 + +#define RF_LQI_CRC_OK (1 << 7) +#define RF_LQI_LQI_EST_MASK (0x7f) + +__xdata __at (0xdf3a) uint8_t RF_RSSI; +#define RF_RSSI_OFF 0x3a + +__xdata __at (0xdf3b) uint8_t RF_MARCSTATE; +#define RF_MARCSTATE_OFF 0x3b + +#define RF_MARCSTATE_MASK 0x0f +#define RF_MARCSTATE_SLEEP 0x00 +#define RF_MARCSTATE_IDLE 0x01 +#define RF_MARCSTATE_VCOON_MC 0x03 +#define RF_MARCSTATE_REGON_MC 0x04 +#define RF_MARCSTATE_MANCAL 0x05 +#define RF_MARCSTATE_VCOON 0x06 +#define RF_MARCSTATE_REGON 0x07 +#define RF_MARCSTATE_STARTCAL 0x08 +#define RF_MARCSTATE_BWBOOST 0x09 +#define RF_MARCSTATE_FS_LOCK 0x0a +#define RF_MARCSTATE_IFADCON 0x0b +#define RF_MARCSTATE_ENDCAL 0x0c +#define RF_MARCSTATE_RX 0x0d +#define RF_MARCSTATE_RX_END 0x0e +#define RF_MARCSTATE_RX_RST 0x0f +#define RF_MARCSTATE_TXRX_SWITCH 0x10 +#define RF_MARCSTATE_RX_OVERFLOW 0x11 +#define RF_MARCSTATE_FSTXON 0x12 +#define RF_MARCSTATE_TX 0x13 +#define RF_MARCSTATE_TX_END 0x14 +#define RF_MARCSTATE_RXTX_SWITCH 0x15 +#define RF_MARCSTATE_TX_UNDERFLOW 0x16 + + +__xdata __at (0xdf3c) uint8_t RF_PKTSTATUS; +#define RF_PKTSTATUS_OFF 0x3c + +#define RF_PKTSTATUS_CRC_OK (1 << 7) +#define RF_PKTSTATUS_CS (1 << 6) +#define RF_PKTSTATUS_PQT_REACHED (1 << 5) +#define RF_PKTSTATUS_CCA (1 << 4) +#define RF_PKTSTATUS_SFD (1 << 3) + +__xdata __at (0xdf3d) uint8_t RF_VCO_VC_DAC; +#define RF_VCO_VC_DAC_OFF 0x3d + +#define PACKET_LEN 128 + +void +radio_init(void); + +void +delay (unsigned char n); diff --git a/target/radio/recv.c b/target/radio/recv.c new file mode 100644 index 00000000..17a3d178 --- /dev/null +++ b/target/radio/recv.c @@ -0,0 +1,66 @@ +/* + * Copyright © 2008 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include "radio.h" + +main () +{ + static uint8_t packet[PACKET_LEN + 2]; + CLKCON = 0; + while (!(SLEEP & SLEEP_XOSC_STB)) + ; + /* Set P2_0 to output */ + P1 = 0; + P1DIR = 0x02; + radio_init (); + delay(100); + + for (;;) { + uint8_t i; + RFST = RFST_SIDLE; + RFIF = 0; + delay(100); + RFST = RFST_SRX; +// while (!(RFIF & RFIF_IM_CS)); +// P1 = 2; + for (i = 0; i < PACKET_LEN + 2; i++) { + while (!RFTXRXIF) + ; + P1=2; + RFTXRXIF = 0; + packet[i] = RFD; + } + P1 = 0; + + /* check packet contents */ + for (i = 0; i < PACKET_LEN; i++) + if (packet[i] != i) + break; + + /* get excited if the packet came through correctly */ + if (i == PACKET_LEN) { + for (i = 0; i < 3; i++){ + P1 = 2; + delay(100); + P1 = 0; + delay(100); + } + } + delay(100); + } +} diff --git a/target/radio/xmit.c b/target/radio/xmit.c new file mode 100644 index 00000000..e80a0f8b --- /dev/null +++ b/target/radio/xmit.c @@ -0,0 +1,47 @@ +/* + * Copyright © 2009 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include "radio.h" + +main () +{ + int16_t j; + CLKCON = 0; + while (!(SLEEP & SLEEP_XOSC_STB)) + ; + P1 = 0; + P1DIR = 3; + radio_init (); + delay(100); + + for (;;) { + uint8_t i; + + for (j = 0; j < 100; j++) + delay(100); + P1 = 2; + RFST = RFST_SIDLE; + delay(1); + RFST = RFST_STX; + for (i = 0; i < PACKET_LEN; i++) { + while (!RFTXRXIF); + RFTXRXIF = 0; + RFD = i; + } + P1 = 0; + } +} -- cgit v1.2.3 From 94e5343a72121a81ab19bf5025e6b6fc9847eb4f Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 17 Apr 2009 10:19:25 -0700 Subject: Add packet status byte defines --- target/radio/radio.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'target') diff --git a/target/radio/radio.h b/target/radio/radio.h index d501ad12..f68001e4 100644 --- a/target/radio/radio.h +++ b/target/radio/radio.h @@ -109,6 +109,13 @@ __xdata __at (0xdf03) uint8_t RF_PKTCTRL1; #define PKTCTRL1_ADR_CHK_00_BROADCAST (2 << 0) #define PKTCTRL1_ADR_CHK_00_FF_BROADCAST (3 << 0) +/* If APPEND_STATUS is used, two bytes will be added to the packet data */ +#define PKT_APPEND_STATUS_0_RSSI_MASK (0xff) +#define PKT_APPEND_STATUS_0_RSSI_SHIFT 0 +#define PKT_APPEND_STATUS_1_CRC_OK (1 << 7) +#define PKT_APPEND_STATUS_1_LQI_MASK (0x7f) +#define PKT_APPEND_STATUS_1_LQI_SHIFT 0 + __xdata __at (0xdf04) uint8_t RF_PKTCTRL0; #define RF_PKTCTRL0_OFF 0x04 #define RF_PKTCTRL0_WHITE_DATA (1 << 6) -- cgit v1.2.3 From 20834caf01ddf481e8362b0d2627ef383a82e09d Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 17 Apr 2009 10:23:10 -0700 Subject: Add data whitening --- target/radio/init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'target') diff --git a/target/radio/init.c b/target/radio/init.c index 61efb347..6843ef9a 100644 --- a/target/radio/init.c +++ b/target/radio/init.c @@ -157,7 +157,8 @@ static __code uint8_t radio_setup[] = { RF_PKTCTRL1_OFF, ((1 << PKTCTRL1_PQT_SHIFT)| PKTCTRL1_APPEND_STATUS| PKTCTRL1_ADR_CHK_NONE), - RF_PKTCTRL0_OFF, (RF_PKTCTRL0_PKT_FORMAT_NORMAL| + RF_PKTCTRL0_OFF, (RF_PKTCTRL0_WHITE_DATA| + RF_PKTCTRL0_PKT_FORMAT_NORMAL| RF_PKTCTRL0_LENGTH_CONFIG_FIXED), RF_ADDR_OFF, 0x00, RF_MCSM2_OFF, (RF_MCSM2_RX_TIME_END_OF_PACKET), -- cgit v1.2.3 From 293a357911090a2f37bdd6f7ea96942079ffdf2e Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 17 Apr 2009 10:29:42 -0700 Subject: Add CRC to radio packets --- target/radio/init.c | 1 + target/radio/recv.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'target') diff --git a/target/radio/init.c b/target/radio/init.c index 6843ef9a..6349e16d 100644 --- a/target/radio/init.c +++ b/target/radio/init.c @@ -159,6 +159,7 @@ static __code uint8_t radio_setup[] = { PKTCTRL1_ADR_CHK_NONE), RF_PKTCTRL0_OFF, (RF_PKTCTRL0_WHITE_DATA| RF_PKTCTRL0_PKT_FORMAT_NORMAL| + RF_PKTCTRL0_CRC_EN| RF_PKTCTRL0_LENGTH_CONFIG_FIXED), RF_ADDR_OFF, 0x00, RF_MCSM2_OFF, (RF_MCSM2_RX_TIME_END_OF_PACKET), diff --git a/target/radio/recv.c b/target/radio/recv.c index 17a3d178..1f50d8a9 100644 --- a/target/radio/recv.c +++ b/target/radio/recv.c @@ -53,8 +53,10 @@ main () break; /* get excited if the packet came through correctly */ - if (i == PACKET_LEN) { - for (i = 0; i < 3; i++){ + if (i == PACKET_LEN && + packet[PACKET_LEN+1] & PKT_APPEND_STATUS_1_CRC_OK) + { + for (i = 0; i < 5; i++){ P1 = 2; delay(100); P1 = 0; -- cgit v1.2.3 From 31fce622b1bab7e3f421069d7f6d4d9bdcd825de Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 17 Apr 2009 10:32:45 -0700 Subject: Enable FEC in radio packets --- target/radio/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/radio/init.c b/target/radio/init.c index 6349e16d..c9b3d186 100644 --- a/target/radio/init.c +++ b/target/radio/init.c @@ -117,7 +117,7 @@ static __code uint8_t radio_setup[] = { RF_MDMCFG2_OFF, (RF_MDMCFG2_DEM_DCFILT_OFF | RF_MDMCFG2_MOD_FORMAT_GFSK | RF_MDMCFG2_SYNC_MODE_15_16_THRES), - RF_MDMCFG1_OFF, (RF_MDMCFG1_FEC_DIS | + RF_MDMCFG1_OFF, (RF_MDMCFG1_FEC_EN | RF_MDMCFG1_NUM_PREAMBLE_4 | (2 << RF_MDMCFG1_CHANSPC_E_SHIFT)), RF_MDMCFG0_OFF, (17 << RF_MDMCFG0_CHANSPC_M_SHIFT), -- cgit v1.2.3