From f7ca88282466c271bad5e25e804729580fe83c47 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 11 Sep 2018 01:28:03 -0700 Subject: altos/stm32f4: Fix clock configuration Was running the PLL input too slow (it wants 2MHz). Was configuring the PLL_P factor wrong (needs magic values, not P value) Set up clock debugging for PA8 and PC9 output. Enable on disco board for debugging. Signed-off-by: Keith Packard --- src/stm32f4-disco/ao_pins.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/stm32f4-disco') diff --git a/src/stm32f4-disco/ao_pins.h b/src/stm32f4-disco/ao_pins.h index 3bbace1a..c4dc5b4b 100644 --- a/src/stm32f4-disco/ao_pins.h +++ b/src/stm32f4-disco/ao_pins.h @@ -27,9 +27,9 @@ #define AO_HSE 8000000 /* fed from st/link processor */ #define AO_HSE_BYPASS 1 /* no xtal, directly fed */ -#define AO_PLL_M 8 /* down to 1MHz */ +#define AO_PLL_M 4 /* down to 2MHz */ -#define AO_PLL1_N 192 /* up to 192MHz */ +#define AO_PLL1_N 96 /* up to 192MHz */ #define AO_PLL1_P 2 /* down to 96MHz */ #define AO_PLL1_Q 4 /* down to 48MHz for USB and SDIO */ @@ -41,4 +41,6 @@ #define AO_APB2_PRESCALER 1 #define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_1 +#define DEBUG_THE_CLOCK 1 + #endif /* _AO_PINS_H_ */ -- cgit v1.2.3