From 6802b6a65b1fec06c2c873282be792c40b3c8f5e Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 28 Aug 2013 22:10:58 -0600 Subject: altos/stm: Remove stale timer defines Stuff from when we weren't using systick Signed-off-by: Keith Packard --- src/stm/ao_timer.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'src/stm/ao_timer.c') diff --git a/src/stm/ao_timer.c b/src/stm/ao_timer.c index daf2f400..5cf1e4a8 100644 --- a/src/stm/ao_timer.c +++ b/src/stm/ao_timer.c @@ -67,20 +67,6 @@ ao_timer_set_adc_interval(uint8_t interval) } #endif -/* - * According to the STM clock-configuration, timers run - * twice as fast as the APB1 clock *if* the APB1 prescaler - * is greater than 1. - */ - -#if AO_APB1_PRESCALER > 1 -#define TIMER_23467_SCALER 2 -#else -#define TIMER_23467_SCALER 1 -#endif - -#define TIMER_10kHz ((AO_PCLK1 * TIMER_23467_SCALER) / 10000) - #define SYSTICK_RELOAD (AO_SYSTICK / 100 - 1) void -- cgit v1.2.3 From 7c82acc1c1c5b7b4da7c7ecb3b2fd90140e4c703 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 28 Aug 2013 22:12:25 -0600 Subject: altos/stm: Make sure we switch to MSI during timer init Need to ensure that the CPU is actually using the MSI during timer init or all of the other clock changes won't work Signed-off-by: Keith Packard --- src/stm/ao_timer.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'src/stm/ao_timer.c') diff --git a/src/stm/ao_timer.c b/src/stm/ao_timer.c index 5cf1e4a8..34f9edb9 100644 --- a/src/stm/ao_timer.c +++ b/src/stm/ao_timer.c @@ -90,7 +90,15 @@ ao_clock_init(void) /* Switch to MSI while messing about */ stm_rcc.cr |= (1 << STM_RCC_CR_MSION); while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY))) - asm("nop"); + ao_arch_nop(); + + stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) | + (STM_RCC_CFGR_SW_MSI << STM_RCC_CFGR_SW); + + /* wait for system to switch to MSI */ + while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) != + (STM_RCC_CFGR_SWS_MSI << STM_RCC_CFGR_SWS)) + ao_arch_nop(); /* reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE */ stm_rcc.cfgr &= (uint32_t)0x88FFC00C; @@ -141,7 +149,6 @@ ao_clock_init(void) stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN); /* Enable 1 wait state so the CPU can run at 32MHz */ - /* (haven't managed to run the CPU at 32MHz yet, it's at 16MHz) */ stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY); /* Enable power interface clock */ -- cgit v1.2.3