| Commit message (Collapse) | Author | Age |
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The textram section must be aligned to 8 bytes to keep the linker
happy. However, if that section contains no data, the declaration will
set the __data_start__ value to that alignment, but the data section
itself would start on a 4-byte alignment, potentially 4 bytes lower
than the value indicated by __data_start__. This completely scrambles
initialized memory as the startup code will copy the data segment to
__data_start__, 4 bytes off of the actual data segment start.
Fix this by forcing the data segment to also be aligned to 8 bytes.
Signed-off-by: Keith Packard <keithp@keithp.com>
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The ring is updated when the ADC finishes; all of the other sensor
data needs to be copied in at that point.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Redefines some stdio bits so that we can build with either pdclib or
newlib + avr stdio.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Signed-off-by: Keith Packard <keithp@keithp.com>
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This is clearer than using '0'.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Signed-off-by: Keith Packard <keithp@keithp.com>
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If you try this after the UART is running, it won't work.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This allows other systems to see what baud rate the host has requested.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Lets cortexelf do more things with groups of pins, rather than one pin
at a time.
Signed-off-by: Keith Packard <keithp@keithp.com>
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ao_gpio_set_mask and ao_gpio_get_all
Signed-off-by: Keith Packard <keithp@keithp.com>
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Scans the matrix once per clock tick queuing events for changed keys.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Signed-off-by: Keith Packard <keithp@keithp.com>
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Signed-off-by: Keith Packard <keithp@keithp.com>
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Signed-off-by: Keith Packard <keithp@keithp.com>
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Signed-off-by: Keith Packard <keithp@keithp.com>
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Just adds the necessary defines to the code.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This lets code which needs finer control over DMA to use the channel
without interference, and leaves the DMA engine running so that it can.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This allows for high priority interrupts (priority 0) to run, even
when other interrupts are blocked. Code executing in such interrupt
handlers must not attempt to control task execution as that will race
with the scheduler.
Select this by defining AO_NONMASK_INTERRUPT in ao_pins.h.
non-maskable interrupt priority is AO_STM_NVIC_NONMASK_PRIORITY
Signed-off-by: Keith Packard <keithp@keithp.com>
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Because the STM32L only offers 16 priority levels, the bottom four
bits of each priority mask are not used. All of the interrupt priority
settings in the system were using values < 16, making them all
effectively the same. Fix that by moving them into the upper 4 bits
and using symbolic constants everywhere.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Gcc 5.4.1 tracks alignment of data through assignments, so that a
uint32_t pointer which comes from byte-aligned uint8_t data:
extern uint8_t foo[];
uint32_t *q = (void *) foo;
Fetches and stores through this pointer are done bytewise. This is
slow (meh), but if q references a device register, things to bad very
quickly.
This patch works around this bug in the compiler by adding
__attribute__((aligned(4))) tags to some variables, or changing them
from uint8_t to uint32_t. Places doing this will now be caught as I've
added -Wcast-align to the compiler flags. That required adding (void
*) casts, after the relevant code was checked to make sure the
compiler could tell that the addresses were aligned.
Signed-off-by: Keith Packard <keithp@keithp.com>
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I'm sure this makes the function end up in-lined, which saves enough
text space to fit the flash loader in ROM again.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Set spi slave DMA priority MOSI to HIGH and MISO to VERY_HIGH. Slave
SPI doesn't have the luxury of slowing down when the system is busy,
so provide it maximum memory bandwidth to try and keep up with the
master.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Make sure receive DMA is higher than any TX dma so that
it always runs in preference.
Signed-off-by: Keith Packard <keithp@keithp.com>
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When the MISO DMA priority is too low, and the processor gets busy,
it's possible for SPI input to overrun the processor, which causes the
MISO DMA to get out of sync and never finish. Set the MISO DMA
priority to HIGH to avoid this.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Instead of having nearly duplicate versions of the SPI DMA
configuration calls, create helper funcs that do most of the work so
that the SPI API funcs are shorter and clearer.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Provides a bit better typechecking opportunities for this function.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Signed-off-by: Keith Packard <keithp@keithp.com>
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Was computing (1 << pin) twice for no good reason.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This provides inline functions for sending and receiving individual
bytes, and setup/finish functions to wrap them in. This make the byte
sending respect the SPI hardware interface requirements.
Signed-off-by: Keith Packard <keithp@keithp.com>
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These had an extra level of switch nesting for no good reason.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This regularizes SPI hardware use and ensures that the device is
turned off after it has been used and that the status register is back
to 'normal' the next time through.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This dumps out the SPI hardware state and history of SPI operations
when compiled with -DDEBUG=1. Without that, this patch does nothing.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This provides a command that shows current DMA operations when
compiled with -DDEBUG=1. Without that, this patch has no effect.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Provides for a bit better error checking.
Signed-off-by: Keith Packard <keithp@keithp.com>
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These weren't the original version of the docs that we had.
Signed-off-by: Keith Packard <keithp@keithp.com>
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DMA channels which are 'allocated' can't be shared. Instead of using
the value '1' in the related 'mutex', use 0xff which won't match any task.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This function isn't used anywhere.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Interrupts may not be blocked in the timer ISR, but they need to be
while walking the pending timer list and moving tasks back to the run
queue.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Just like lpc and stmf0, deal with the host resetting the bus while
rebooting by restoring all usb-related data to the initial values.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This reverts commit 6a9546413d6a236c010e806b50506d870961d074.
This causes the device to stop reliably handling interrupts.
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This allows applications to request that the flow control bits be
driven from software rather than hardware, permitting more flexible
pin configuration.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Using TXE allows for full-speed communication, rather than waiting for
each byte to be transmitted before inserting the next into the queue.
Signed-off-by: Keith Packard <keithp@keithp.com>
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These set or clear a group of bits in a single GPIO register all together.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This allows for SPI output at interrupt time, one byte at a time.
Signed-off-by: Keith Packard <keithp@keithp.com>
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While 512 bytes is a reasonable size, sometimes apps don't have that
much stack space.
Signed-off-by: Keith Packard <keithp@keithp.com>
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We use a separate stack pointer for task code, which means we can
verify that it is in range in any interrupt handler. This adds checks
for the task stack (under #ifdef DEBUG) that run in ao_wakeup as well
as at every timer interrupt.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This provides a bit more room for tasks on their stack
Signed-off-by: Keith Packard <keithp@keithp.com>
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This allows multiple SoCs to provide the same driver interface
Signed-off-by: Keith Packard <keithp@keithp.com>
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Fix the CCMR1_OC1PE and CCMR2_OC3PE values.
Disable clock when no PWM outputs are running.
Fix the apb1enr value for the timer.
Set ARR value to PWM_MAX - 1 -- ARR is off by one.
Sets the GPIO pins to 40MHz bandwidth for sharper edges.
Tested on EasyMega, but that code is not included as it breaks the
companion protocol.
Signed-off-by: Keith Packard <keithp@keithp.com>
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