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-rw-r--r--target/adc-serial/adc_serial.c6
-rw-r--r--target/adc/adc.c6
-rw-r--r--target/beep-timer/beep_timer.c4
-rw-r--r--target/dma/dma.c4
-rw-r--r--target/ee/ee.c6
-rw-r--r--target/isr.c1
-rw-r--r--target/radio/init.c4
-rw-r--r--target/radio/recv.c2
-rw-r--r--target/serial/serial.c4
-rw-r--r--target/timer/cc1111.h70
10 files changed, 53 insertions, 54 deletions
diff --git a/target/adc-serial/adc_serial.c b/target/adc-serial/adc_serial.c
index eba58744..1f7b6880 100644
--- a/target/adc-serial/adc_serial.c
+++ b/target/adc-serial/adc_serial.c
@@ -427,7 +427,7 @@ adc_init(void)
dma_config.cfg1 = (DMA_CFG1_SRCINC_0 |
DMA_CFG1_DESTINC_1 |
DMA_CFG1_PRIORITY_NORMAL);
-
+
dma_config.src_high = ADDRH(&ADCXDATA);
dma_config.src_low = ADDRL(&ADCXDATA);
dma_config.dst_high = ADDRH(adc_output);
@@ -442,7 +442,7 @@ adc_init(void)
(1 << 3) | /* battery voltage */
(1 << 4) | /* drogue sense */
(1 << 5)); /* main sense */
-
+
ADCCON1 = (ADCCON1_STSEL_START); /* ST bit triggers */
ADCCON2 = (ADCCON2_SREF_VDD | /* reference voltage is VDD */
ADCCON2_SDIV_512 | /* 12 bit ADC results */
@@ -554,7 +554,7 @@ main ()
CLKCON = 0;
while (!(SLEEP & SLEEP_XOSC_STB))
;
-
+
adc_init();
P1_0 = 1;
usart_init();
diff --git a/target/adc/adc.c b/target/adc/adc.c
index bdc6c614..3a63a2c6 100644
--- a/target/adc/adc.c
+++ b/target/adc/adc.c
@@ -419,7 +419,7 @@ adc_init(void)
dma_config.cfg1 = (DMA_CFG1_SRCINC_0 |
DMA_CFG1_DESTINC_1 |
DMA_CFG1_PRIORITY_NORMAL);
-
+
dma_config.src_high = ADDRH(&ADCXDATA);
dma_config.src_low = ADDRL(&ADCXDATA);
dma_config.dst_high = ADDRH(adc_output);
@@ -434,7 +434,7 @@ adc_init(void)
(1 << 3) | /* battery voltage */
(1 << 4) | /* drogue sense */
(1 << 5)); /* main sense */
-
+
ADCCON1 = (ADCCON1_STSEL_START); /* ST bit triggers */
ADCCON2 = (ADCCON2_SREF_VDD | /* reference voltage is VDD */
ADCCON2_SDIV_512 | /* 12 bit ADC results */
@@ -460,7 +460,7 @@ main ()
;
while (P1 & 0x4)
;
-
+
adc_init();
for (;;) {
adc_run();
diff --git a/target/beep-timer/beep_timer.c b/target/beep-timer/beep_timer.c
index 53b95495..b3fa8754 100644
--- a/target/beep-timer/beep_timer.c
+++ b/target/beep-timer/beep_timer.c
@@ -87,7 +87,7 @@ sfr at 0xCA T3CNT;
sfr at 0xEA T4CNT;
/* Timer control */
-
+
sfr at 0xCB T3CTL;
sfr at 0xEB T4CTL;
@@ -189,7 +189,7 @@ main ()
T4CCTL0 = TxCCTLy_CMP_TOGGLE|TxCCTLy_CMP_MODE_ENABLE;
T4CC0 = 125;
T4CTL = TxCTL_DIV_32 | TxCTL_MODE_MODULO;
-
+
for (;;) {
___ _ ___ _ C ___ ___ _ ___ W /* cq */
___ _ _ C _ W /* de */
diff --git a/target/dma/dma.c b/target/dma/dma.c
index c35c39f6..1762b658 100644
--- a/target/dma/dma.c
+++ b/target/dma/dma.c
@@ -322,7 +322,7 @@ dma_init(void)
config.cfg1 = (DMA_CFG1_SRCINC_1 |
DMA_CFG1_DESTINC_1 |
DMA_CFG1_PRIORITY_NORMAL);
-
+
config.src_high = ADDRH(dma_input);
config.src_low = ADDRL(dma_input);
config.dst_high = ADDRH(dma_output);
@@ -351,7 +351,7 @@ main ()
CLKCON = 0;
while (!(SLEEP & SLEEP_XOSC_STB))
;
-
+
dma_init();
dma_run();
for (;;) {
diff --git a/target/ee/ee.c b/target/ee/ee.c
index 7cc47120..9ea22cdc 100644
--- a/target/ee/ee.c
+++ b/target/ee/ee.c
@@ -174,7 +174,7 @@ uint8_t
bitbang_in_bit(void)
{
uint8_t b;
-
+
delay(1);
SCK = 1;
delay(1);
@@ -319,7 +319,7 @@ wrsr(uint8_t status)
spi_out_byte(status);
spi_cs(1);
}
-
+
void
wren(void)
{
@@ -385,7 +385,7 @@ main ()
CLKCON = 0;
while (!(SLEEP & SLEEP_XOSC_STB))
;
-
+
spi_init();
status = rdsr();
diff --git a/target/isr.c b/target/isr.c
index 43aedc29..ae4d04c5 100644
--- a/target/isr.c
+++ b/target/isr.c
@@ -87,4 +87,3 @@ void rf_isr (void) __interrupt(16) __using(1)
void wdt_isr (void) __interrupt(17) __using(1)
{
}
-
diff --git a/target/radio/init.c b/target/radio/init.c
index c9b3d186..ea7c984c 100644
--- a/target/radio/init.c
+++ b/target/radio/init.c
@@ -106,7 +106,7 @@ static __code uint8_t radio_setup[] = {
RF_FREQ2_OFF, FREQ_CONTROL >> 16,
RF_FREQ1_OFF, FREQ_CONTROL >> 8,
RF_FREQ0_OFF, FREQ_CONTROL >> 0,
-
+
RF_FSCTRL1_OFF, (IF_FREQ_CONTROL << RF_FSCTRL1_FREQ_IF_SHIFT),
RF_FSCTRL0_OFF, (0 << RF_FSCTRL0_FREQOFF_SHIFT),
@@ -150,7 +150,7 @@ static __code uint8_t radio_setup[] = {
/* default sync values */
RF_SYNC1_OFF, 0xD3,
RF_SYNC0_OFF, 0x91,
-
+
/* max packet length */
RF_PKTLEN_OFF, PACKET_LEN,
diff --git a/target/radio/recv.c b/target/radio/recv.c
index 1f50d8a9..c50c3205 100644
--- a/target/radio/recv.c
+++ b/target/radio/recv.c
@@ -46,7 +46,7 @@ main ()
packet[i] = RFD;
}
P1 = 0;
-
+
/* check packet contents */
for (i = 0; i < PACKET_LEN; i++)
if (packet[i] != i)
diff --git a/target/serial/serial.c b/target/serial/serial.c
index 29390426..63f6c6de 100644
--- a/target/serial/serial.c
+++ b/target/serial/serial.c
@@ -259,12 +259,12 @@ main ()
CLKCON = 0;
while (!(SLEEP & SLEEP_XOSC_STB))
;
-
+
usart_init();
for (;;) {
usart_out_string("hello world\r\n");
debug_byte(usart_in_byte());
}
-
+
}
diff --git a/target/timer/cc1111.h b/target/timer/cc1111.h
index 7a531cc0..76c95c27 100644
--- a/target/timer/cc1111.h
+++ b/target/timer/cc1111.h
@@ -2,23 +2,23 @@
Register Declarations for the ChipCon CC1111 Processor Range
Copyright © 2008 Keith Packard <keithp@keithp.com>
-
+
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
-
+
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
-
+
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
Adapted from the Cygnal C8051F12x config file which is:
-
+
Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or
@@ -135,37 +135,37 @@ sfr at 0xDD T1CC1H ; /* */
sfr at 0xDE T1CC2L ; /* */
sfr at 0xDF T1CC2H ; /* */
sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE1 RFST ; /* */
-sfr at 0xE2 T1CNTL ; /* */
-sfr at 0xE3 T1CNTH ; /* */
-sfr at 0xE4 T1CTL ; /* */
-sfr at 0xE5 T1CCTL0 ; /* */
-sfr at 0xE6 T1CCTL1 ; /* */
-sfr at 0xE7 T1CCTL2 ; /* */
-sfr at 0xE8 IRCON2 ; /* */
-sfr at 0xE9 RFIF ; /* */
-sfr at 0xEA T4CNT ; /* */
-sfr at 0xEB T4CTL ; /* */
-sfr at 0xEC T4CCTL0 ; /* */
-sfr at 0xED T4CC0 ; /* */
-sfr at 0xEE T4CCTL1 ; /* */
-sfr at 0xEF T4CC1 ; /* */
-sfr at 0xF0 B ; /* */
-sfr at 0xF1 PERCFG ; /* */
-sfr at 0xF2 ADCCFG ; /* */
-sfr at 0xF3 P0SEL ; /* */
-sfr at 0xF4 P1SEL ; /* */
-sfr at 0xF5 P2SEL ; /* */
-sfr at 0xF6 P1INP ; /* */
-sfr at 0xF7 P2INP ; /* */
-sfr at 0xF8 U1CSR ; /* */
-sfr at 0xF9 U1DBUF ; /* */
-sfr at 0xFA U1BAUD ; /* */
-sfr at 0xFB U1UCR ; /* */
-sfr at 0xFC U1GCR ; /* */
-sfr at 0xFD P0DIR ; /* */
-sfr at 0xFE P1DIR ; /* */
-sfr at 0xFF P2DIR ; /* */
+sfr at 0xE1 RFST ; /* */
+sfr at 0xE2 T1CNTL ; /* */
+sfr at 0xE3 T1CNTH ; /* */
+sfr at 0xE4 T1CTL ; /* */
+sfr at 0xE5 T1CCTL0 ; /* */
+sfr at 0xE6 T1CCTL1 ; /* */
+sfr at 0xE7 T1CCTL2 ; /* */
+sfr at 0xE8 IRCON2 ; /* */
+sfr at 0xE9 RFIF ; /* */
+sfr at 0xEA T4CNT ; /* */
+sfr at 0xEB T4CTL ; /* */
+sfr at 0xEC T4CCTL0 ; /* */
+sfr at 0xED T4CC0 ; /* */
+sfr at 0xEE T4CCTL1 ; /* */
+sfr at 0xEF T4CC1 ; /* */
+sfr at 0xF0 B ; /* */
+sfr at 0xF1 PERCFG ; /* */
+sfr at 0xF2 ADCCFG ; /* */
+sfr at 0xF3 P0SEL ; /* */
+sfr at 0xF4 P1SEL ; /* */
+sfr at 0xF5 P2SEL ; /* */
+sfr at 0xF6 P1INP ; /* */
+sfr at 0xF7 P2INP ; /* */
+sfr at 0xF8 U1CSR ; /* */
+sfr at 0xF9 U1DBUF ; /* */
+sfr at 0xFA U1BAUD ; /* */
+sfr at 0xFB U1UCR ; /* */
+sfr at 0xFC U1GCR ; /* */
+sfr at 0xFD P0DIR ; /* */
+sfr at 0xFE P1DIR ; /* */
+sfr at 0xFF P2DIR ; /* */
/* BIT Registers */