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-rw-r--r--src/stmf0/Makefile-flash.defs2
-rw-r--r--src/stmf0/altos-loader.ld3
-rw-r--r--src/stmf0/altos.ld3
-rw-r--r--src/stmf0/ao_adc_fast.c5
-rw-r--r--src/stmf0/ao_adc_fast.h3
-rw-r--r--src/stmf0/ao_arch.h18
-rw-r--r--src/stmf0/ao_arch_funcs.h55
-rw-r--r--src/stmf0/ao_boot_chain.c3
-rw-r--r--src/stmf0/ao_boot_pin.c3
-rw-r--r--src/stmf0/ao_crc.h3
-rw-r--r--src/stmf0/ao_crc_stm.c3
-rw-r--r--src/stmf0/ao_dma_stm.c3
-rw-r--r--src/stmf0/ao_exti.h3
-rw-r--r--src/stmf0/ao_exti_stm.c3
-rw-r--r--src/stmf0/ao_flash.h3
-rw-r--r--src/stmf0/ao_flash_loader_stm.c3
-rw-r--r--src/stmf0/ao_flash_stm.c3
-rw-r--r--src/stmf0/ao_flash_stm_pins.h3
-rw-r--r--src/stmf0/ao_gpio.c3
-rw-r--r--src/stmf0/ao_interrupt.c3
-rw-r--r--src/stmf0/ao_led.c3
-rw-r--r--src/stmf0/ao_pwm.c3
-rw-r--r--src/stmf0/ao_romconfig.c3
-rw-r--r--src/stmf0/ao_spi_stm.c366
-rw-r--r--src/stmf0/ao_timer.c39
-rw-r--r--src/stmf0/ao_usb_stm.c3
-rw-r--r--src/stmf0/stm32f0.h330
27 files changed, 673 insertions, 202 deletions
diff --git a/src/stmf0/Makefile-flash.defs b/src/stmf0/Makefile-flash.defs
index 29d6ae45..804595bd 100644
--- a/src/stmf0/Makefile-flash.defs
+++ b/src/stmf0/Makefile-flash.defs
@@ -60,7 +60,7 @@ $(OBJ): $(INC)
distclean: clean
clean:
- rm -f *.o $(HARDWARE)-$(PROGNAME)-*.elf
+ rm -f *.o $(HARDWARE)-$(PROGNAME)-*.elf $(HARDWARE)-$(PROGNAME)-*.bin
rm -f ao_product.h
install:
diff --git a/src/stmf0/altos-loader.ld b/src/stmf0/altos-loader.ld
index 86cf1838..c458116b 100644
--- a/src/stmf0/altos-loader.ld
+++ b/src/stmf0/altos-loader.ld
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/altos.ld b/src/stmf0/altos.ld
index 9dbc83d0..8f8933c6 100644
--- a/src/stmf0/altos.ld
+++ b/src/stmf0/altos.ld
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_adc_fast.c b/src/stmf0/ao_adc_fast.c
index 0a2e2c5c..5ce3a396 100644
--- a/src/stmf0/ao_adc_fast.c
+++ b/src/stmf0/ao_adc_fast.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -153,7 +154,7 @@ ao_adc_init(void)
#endif
/* Set the clock */
- stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
+ stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_ADCCLK << STM_ADC_CFGR2_CKMODE;
/* Shortest sample time */
stm_adc.smpr = STM_ADC_SMPR_SMP_1_5 << STM_ADC_SMPR_SMP;
diff --git a/src/stmf0/ao_adc_fast.h b/src/stmf0/ao_adc_fast.h
index c6903e9f..b8b5e003 100644
--- a/src/stmf0/ao_adc_fast.h
+++ b/src/stmf0/ao_adc_fast.h
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_arch.h b/src/stmf0/ao_arch.h
index 2597cadc..a36482b6 100644
--- a/src/stmf0/ao_arch.h
+++ b/src/stmf0/ao_arch.h
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -114,21 +115,14 @@ extern const uint32_t ao_radio_cal;
#endif
#define AO_HCLK (AO_SYSCLK / AO_AHB_PRESCALER)
-#define AO_PCLK1 (AO_HCLK / AO_APB1_PRESCALER)
-#define AO_PCLK2 (AO_HCLK / AO_APB2_PRESCALER)
+#define AO_PCLK (AO_HCLK / AO_APB_PRESCALER)
#define AO_SYSTICK (AO_HCLK)
#define AO_PANIC_DELAY_SCALE (AO_SYSCLK / 12000000)
-#if AO_APB1_PRESCALER == 1
-#define AO_TIM23467_CLK AO_PCLK1
+#if AO_APB_PRESCALER == 1
+#define AO_TIM_CLK AO_PCLK
#else
-#define AO_TIM23467_CLK (2 * AO_PCLK1)
-#endif
-
-#if AO_APB2_PRESCALER == 1
-#define AO_TIM91011_CLK AO_PCLK2
-#else
-#define AO_TIM91011_CLK (2 * AO_PCLK2)
+#define AO_TIM_CLK (2 * AO_PCLK)
#endif
#define AO_STM_NVIC_HIGH_PRIORITY (0 << 6)
diff --git a/src/stmf0/ao_arch_funcs.h b/src/stmf0/ao_arch_funcs.h
index 64311b23..8b6234c4 100644
--- a/src/stmf0/ao_arch_funcs.h
+++ b/src/stmf0/ao_arch_funcs.h
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -82,7 +83,57 @@ void
ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
void
-ao_spi_send_sync(void *block, uint16_t len, uint8_t spi_index);
+ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
+
+void
+ao_spi_start_bytes(uint8_t spi_index);
+
+void
+ao_spi_stop_bytes(uint8_t spi_index);
+
+static inline void
+ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
+{
+ struct stm_spi *stm_spi;
+
+ switch (AO_SPI_INDEX(spi_index)) {
+ case 0:
+ stm_spi = &stm_spi1;
+ break;
+ case 1:
+ stm_spi = &stm_spi2;
+ break;
+ }
+
+ while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
+ ;
+ stm_spi->dr = byte;
+ while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
+ ;
+ (void) stm_spi->dr;
+}
+
+static inline uint8_t
+ao_spi_recv_byte(uint8_t spi_index)
+{
+ struct stm_spi *stm_spi;
+
+ switch (AO_SPI_INDEX(spi_index)) {
+ case 0:
+ stm_spi = &stm_spi1;
+ break;
+ case 1:
+ stm_spi = &stm_spi2;
+ break;
+ }
+
+ while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
+ ;
+ stm_spi->dr = 0xff;
+ while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
+ ;
+ return stm_spi->dr;
+}
void
ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
diff --git a/src/stmf0/ao_boot_chain.c b/src/stmf0/ao_boot_chain.c
index 83a543a0..8f850a0a 100644
--- a/src/stmf0/ao_boot_chain.c
+++ b/src/stmf0/ao_boot_chain.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_boot_pin.c b/src/stmf0/ao_boot_pin.c
index e825b618..4b5dc2ac 100644
--- a/src/stmf0/ao_boot_pin.c
+++ b/src/stmf0/ao_boot_pin.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_crc.h b/src/stmf0/ao_crc.h
index cd011d3a..7acc6f9c 100644
--- a/src/stmf0/ao_crc.h
+++ b/src/stmf0/ao_crc.h
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_crc_stm.c b/src/stmf0/ao_crc_stm.c
index 863f5ef5..4eb4540e 100644
--- a/src/stmf0/ao_crc_stm.c
+++ b/src/stmf0/ao_crc_stm.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_dma_stm.c b/src/stmf0/ao_dma_stm.c
index e90c6bf8..7045514c 100644
--- a/src/stmf0/ao_dma_stm.c
+++ b/src/stmf0/ao_dma_stm.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_exti.h b/src/stmf0/ao_exti.h
index 192611bd..7452af8e 100644
--- a/src/stmf0/ao_exti.h
+++ b/src/stmf0/ao_exti.h
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_exti_stm.c b/src/stmf0/ao_exti_stm.c
index 910afcf7..910a36f2 100644
--- a/src/stmf0/ao_exti_stm.c
+++ b/src/stmf0/ao_exti_stm.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_flash.h b/src/stmf0/ao_flash.h
index 09ca5ac1..d191d80d 100644
--- a/src/stmf0/ao_flash.h
+++ b/src/stmf0/ao_flash.h
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_flash_loader_stm.c b/src/stmf0/ao_flash_loader_stm.c
index 6bf89234..a8d1701b 100644
--- a/src/stmf0/ao_flash_loader_stm.c
+++ b/src/stmf0/ao_flash_loader_stm.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_flash_stm.c b/src/stmf0/ao_flash_stm.c
index 5fe0e619..2aeff388 100644
--- a/src/stmf0/ao_flash_stm.c
+++ b/src/stmf0/ao_flash_stm.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_flash_stm_pins.h b/src/stmf0/ao_flash_stm_pins.h
index ab60b4f3..80993b24 100644
--- a/src/stmf0/ao_flash_stm_pins.h
+++ b/src/stmf0/ao_flash_stm_pins.h
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_gpio.c b/src/stmf0/ao_gpio.c
index c7bf0797..024ff948 100644
--- a/src/stmf0/ao_gpio.c
+++ b/src/stmf0/ao_gpio.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_interrupt.c b/src/stmf0/ao_interrupt.c
index c6d8ef34..79412483 100644
--- a/src/stmf0/ao_interrupt.c
+++ b/src/stmf0/ao_interrupt.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_led.c b/src/stmf0/ao_led.c
index 9b61cf62..0f39befb 100644
--- a/src/stmf0/ao_led.c
+++ b/src/stmf0/ao_led.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_pwm.c b/src/stmf0/ao_pwm.c
index c1e157f5..f1c10b0b 100644
--- a/src/stmf0/ao_pwm.c
+++ b/src/stmf0/ao_pwm.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_romconfig.c b/src/stmf0/ao_romconfig.c
index 5da15072..9d5fd6fb 100644
--- a/src/stmf0/ao_romconfig.c
+++ b/src/stmf0/ao_romconfig.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/ao_spi_stm.c b/src/stmf0/ao_spi_stm.c
index 55bf59d2..0448ad8c 100644
--- a/src/stmf0/ao_spi_stm.c
+++ b/src/stmf0/ao_spi_stm.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -41,8 +42,6 @@ static const struct ao_spi_stm_info ao_spi_stm_info[STM_NUM_SPI] = {
static uint8_t spi_dev_null;
-
-
#define SPI_CR2 ((0 << STM_SPI_CR2_LDMA_TX) | \
(0 << STM_SPI_CR2_LDMA_RX) | \
(1 << STM_SPI_CR2_FRXTH) | \
@@ -62,12 +61,86 @@ static uint8_t spi_dev_null;
(0 << STM_SPI_CR2_TXDMAEN) | \
(0 << STM_SPI_CR2_RXDMAEN))
+#if DEBUG
+static struct {
+ uint8_t task;
+ uint8_t which;
+ AO_TICK_TYPE tick;
+ uint16_t len;
+} spi_tasks[64];
+static uint8_t spi_task_index;
+
+static void
+validate_spi(struct stm_spi *stm_spi, int which, uint16_t len)
+{
+ uint32_t sr = stm_spi->sr;
+
+ if (stm_spi != &stm_spi2)
+ return;
+ spi_tasks[spi_task_index].task = ao_cur_task ? ao_cur_task->task_id : 0;
+ spi_tasks[spi_task_index].which = which;
+ spi_tasks[spi_task_index].tick = ao_time();
+ spi_tasks[spi_task_index].len = len;
+ spi_task_index = (spi_task_index + 1) & (63);
+ if (sr & (1 << STM_SPI_SR_FRE))
+ ao_panic(0x40 | 1);
+ if (sr & (1 << STM_SPI_SR_BSY))
+ ao_panic(0x40 | 2);
+ if (sr & (1 << STM_SPI_SR_OVR))
+ ao_panic(0x40 | 3);
+ if (sr & (1 << STM_SPI_SR_MODF))
+ ao_panic(0x40 | 4);
+ if (sr & (1 << STM_SPI_SR_UDR))
+ ao_panic(0x40 | 5);
+ if ((sr & (1 << STM_SPI_SR_TXE)) == 0)
+ ao_panic(0x40 | 6);
+ if (sr & (1 << STM_SPI_SR_RXNE))
+ ao_panic(0x40 | 7);
+ if (which != 5 && which != 6 && which != 13)
+ if (ao_cur_task->task_id != ao_spi_mutex[1])
+ ao_panic(0x40 | 8);
+}
+#else
+#define validate_spi(stm_spi, which, len) do { (void) (which); (void) (len); } while (0)
+#endif
+
+static void
+ao_spi_run(uint8_t id, uint8_t which, uint16_t len)
+{
+ struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
+ uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
+ uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
+
+ validate_spi(stm_spi, which, len);
+
+ stm_spi->cr2 = SPI_CR2_DMA;
+
+ ao_dma_start(miso_dma_index);
+ ao_dma_start(mosi_dma_index);
+
+ ao_arch_critical(
+ while (!ao_dma_done[miso_dma_index])
+ ao_sleep(&ao_dma_done[miso_dma_index]);
+ );
+
+ while ((stm_spi->sr & (1 << STM_SPI_SR_TXE)) == 0);
+ while (stm_spi->sr & (1 << STM_SPI_SR_BSY));
+
+ validate_spi(stm_spi, which+1, len);
+
+ stm_spi->cr2 = 0;
+
+ ao_dma_done_transfer(mosi_dma_index);
+ ao_dma_done_transfer(miso_dma_index);
+}
+
void
ao_spi_send(const void *block, uint16_t len, uint8_t spi_index)
{
- struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
- uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
- uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
+ uint8_t id = AO_SPI_INDEX(spi_index);
+ struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
+ uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
+ uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
/* Set up the transmit DMA to deliver data */
ao_dma_set_transfer(mosi_dma_index,
@@ -84,9 +157,6 @@ ao_spi_send(const void *block, uint16_t len, uint8_t spi_index)
(STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR) |
(0 << STM_DMA_CCR_TCIE));
- /* Clear RXNE */
- (void) stm_spi->dr;
-
/* Set up the receive DMA -- when this is done, we know the SPI unit
* is idle. Without this, we'd have to poll waiting for the BSY bit to
* be cleared
@@ -105,24 +175,16 @@ ao_spi_send(const void *block, uint16_t len, uint8_t spi_index)
(STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR) |
(1 << STM_DMA_CCR_TCIE));
- stm_spi->cr2 = SPI_CR2_DMA;
-
- ao_dma_start(miso_dma_index);
- ao_dma_start(mosi_dma_index);
- ao_arch_critical(
- while (!ao_dma_done[miso_dma_index])
- ao_sleep(&ao_dma_done[miso_dma_index]);
- );
- ao_dma_done_transfer(mosi_dma_index);
- ao_dma_done_transfer(miso_dma_index);
+ ao_spi_run(id, 1, len);
}
void
ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index)
{
- struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
- uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
- uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
+ uint8_t id = AO_SPI_INDEX(spi_index);
+ struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
+ uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
+ uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
/* Set up the transmit DMA to deliver data */
ao_dma_set_transfer(mosi_dma_index,
@@ -139,9 +201,6 @@ ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index)
(STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR) |
(0 << STM_DMA_CCR_TCIE));
- /* Clear RXNE */
- (void) stm_spi->dr;
-
/* Set up the receive DMA -- when this is done, we know the SPI unit
* is idle. Without this, we'd have to poll waiting for the BSY bit to
* be cleared
@@ -160,40 +219,67 @@ ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index)
(STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR) |
(1 << STM_DMA_CCR_TCIE));
- stm_spi->cr2 = SPI_CR2_DMA;
- ao_dma_start(miso_dma_index);
- ao_dma_start(mosi_dma_index);
- ao_arch_critical(
- while (!ao_dma_done[miso_dma_index])
- ao_sleep(&ao_dma_done[miso_dma_index]);
- );
- ao_dma_done_transfer(mosi_dma_index);
- ao_dma_done_transfer(miso_dma_index);
+ ao_spi_run(id, 3, len);
}
void
-ao_spi_send_sync(void *block, uint16_t len, uint8_t spi_index)
+ao_spi_start_bytes(uint8_t spi_index)
{
- uint8_t *b = block;
- struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
+ uint8_t id = AO_SPI_INDEX(spi_index);
+ struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
stm_spi->cr2 = SPI_CR2_SYNC;
+ validate_spi(stm_spi, 5, 0xffff);
+}
- /* Clear RXNE */
+void
+ao_spi_stop_bytes(uint8_t spi_index)
+{
+ uint8_t id = AO_SPI_INDEX(spi_index);
+ struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
+
+ while ((stm_spi->sr & (1 << STM_SPI_SR_TXE)) == 0)
+ ;
+ while (stm_spi->sr & (1 << STM_SPI_SR_BSY))
+ ;
+ /* Clear the OVR flag */
(void) stm_spi->dr;
+ (void) stm_spi->sr;
+ validate_spi(stm_spi, 6, 0xffff);
+ stm_spi->cr2 = 0;
+}
+void
+ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index)
+{
+ uint8_t id = AO_SPI_INDEX(spi_index);
+ const uint8_t *b = block;
+ struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
+
+ stm_spi->cr2 = SPI_CR2_SYNC;
+
+ validate_spi(stm_spi, 7, len);
while (len--) {
while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)));
stm_spi->dr = *b++;
}
+ while ((stm_spi->sr & (1 << STM_SPI_SR_TXE)) == 0)
+ ;
+ while (stm_spi->sr & (1 << STM_SPI_SR_BSY))
+ ;
+ /* Clear the OVR flag */
+ (void) stm_spi->dr;
+ (void) stm_spi->sr;
+ validate_spi(stm_spi, 8, len);
}
void
ao_spi_recv(void *block, uint16_t len, uint8_t spi_index)
{
- struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
- uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
- uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
+ uint8_t id = AO_SPI_INDEX(spi_index);
+ struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
+ uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
+ uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
spi_dev_null = 0xff;
@@ -212,9 +298,6 @@ ao_spi_recv(void *block, uint16_t len, uint8_t spi_index)
(STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR) |
(0 << STM_DMA_CCR_TCIE));
- /* Clear RXNE */
- (void) stm_spi->dr;
-
/* Set up the receive DMA to capture data */
ao_dma_set_transfer(miso_dma_index,
&stm_spi->dr,
@@ -230,26 +313,16 @@ ao_spi_recv(void *block, uint16_t len, uint8_t spi_index)
(STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR) |
(1 << STM_DMA_CCR_TCIE));
- stm_spi->cr2 = SPI_CR2_DMA;
- ao_dma_start(miso_dma_index);
- ao_dma_start(mosi_dma_index);
-
- /* Wait until the SPI unit is done */
- ao_arch_critical(
- while (!ao_dma_done[miso_dma_index])
- ao_sleep(&ao_dma_done[miso_dma_index]);
- );
-
- ao_dma_done_transfer(mosi_dma_index);
- ao_dma_done_transfer(miso_dma_index);
+ ao_spi_run(id, 9, len);
}
void
ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index)
{
- struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
- uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
- uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
+ uint8_t id = AO_SPI_INDEX(spi_index);
+ struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
+ uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
+ uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
/* Set up transmit DMA to send data */
ao_dma_set_transfer(mosi_dma_index,
@@ -266,9 +339,6 @@ ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index)
(STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR) |
(0 << STM_DMA_CCR_TCIE));
- /* Clear RXNE */
- (void) stm_spi->dr;
-
/* Set up the receive DMA to capture data */
ao_dma_set_transfer(miso_dma_index,
&stm_spi->dr,
@@ -284,18 +354,7 @@ ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index)
(STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR) |
(1 << STM_DMA_CCR_TCIE));
- stm_spi->cr2 = SPI_CR2_DMA;
- ao_dma_start(miso_dma_index);
- ao_dma_start(mosi_dma_index);
-
- /* Wait until the SPI unit is done */
- ao_arch_critical(
- while (!ao_dma_done[miso_dma_index])
- ao_sleep(&ao_dma_done[miso_dma_index]);
- );
-
- ao_dma_done_transfer(mosi_dma_index);
- ao_dma_done_transfer(miso_dma_index);
+ ao_spi_run(id, 11, len);
}
static void
@@ -303,32 +362,24 @@ ao_spi_disable_index(uint8_t spi_index)
{
/* Disable current config
*/
- switch (AO_SPI_INDEX(spi_index)) {
- case STM_SPI_INDEX(1):
- switch (spi_index) {
- case AO_SPI_1_PA5_PA6_PA7:
- stm_gpio_set(&stm_gpioa, 5, 1);
- stm_moder_set(&stm_gpioa, 5, STM_MODER_OUTPUT);
- stm_moder_set(&stm_gpioa, 6, STM_MODER_INPUT);
- stm_moder_set(&stm_gpioa, 7, STM_MODER_OUTPUT);
- break;
- case AO_SPI_1_PB3_PB4_PB5:
- stm_gpio_set(&stm_gpiob, 3, 1);
- stm_moder_set(&stm_gpiob, 3, STM_MODER_OUTPUT);
- stm_moder_set(&stm_gpiob, 4, STM_MODER_INPUT);
- stm_moder_set(&stm_gpiob, 5, STM_MODER_OUTPUT);
- break;
- }
+ switch (spi_index) {
+ case AO_SPI_1_PA5_PA6_PA7:
+ stm_gpio_set(&stm_gpioa, 5, 1);
+ stm_moder_set(&stm_gpioa, 5, STM_MODER_OUTPUT);
+ stm_moder_set(&stm_gpioa, 6, STM_MODER_INPUT);
+ stm_moder_set(&stm_gpioa, 7, STM_MODER_OUTPUT);
break;
- case STM_SPI_INDEX(2):
- switch (spi_index) {
- case AO_SPI_2_PB13_PB14_PB15:
- stm_gpio_set(&stm_gpiob, 13, 1);
- stm_moder_set(&stm_gpiob, 13, STM_MODER_OUTPUT);
- stm_moder_set(&stm_gpiob, 14, STM_MODER_INPUT);
- stm_moder_set(&stm_gpiob, 15, STM_MODER_OUTPUT);
- break;
- }
+ case AO_SPI_1_PB3_PB4_PB5:
+ stm_gpio_set(&stm_gpiob, 3, 1);
+ stm_moder_set(&stm_gpiob, 3, STM_MODER_OUTPUT);
+ stm_moder_set(&stm_gpiob, 4, STM_MODER_INPUT);
+ stm_moder_set(&stm_gpiob, 5, STM_MODER_OUTPUT);
+ break;
+ case AO_SPI_2_PB13_PB14_PB15:
+ stm_gpio_set(&stm_gpiob, 13, 1);
+ stm_moder_set(&stm_gpiob, 13, STM_MODER_OUTPUT);
+ stm_moder_set(&stm_gpiob, 14, STM_MODER_INPUT);
+ stm_moder_set(&stm_gpiob, 15, STM_MODER_OUTPUT);
break;
}
}
@@ -336,29 +387,21 @@ ao_spi_disable_index(uint8_t spi_index)
static void
ao_spi_enable_index(uint8_t spi_index)
{
- switch (AO_SPI_INDEX(spi_index)) {
- case STM_SPI_INDEX(1):
- switch (spi_index) {
- case AO_SPI_1_PA5_PA6_PA7:
- stm_afr_set(&stm_gpioa, 5, STM_AFR_AF0);
- stm_afr_set(&stm_gpioa, 6, STM_AFR_AF0);
- stm_afr_set(&stm_gpioa, 7, STM_AFR_AF0);
- break;
- case AO_SPI_1_PB3_PB4_PB5:
- stm_afr_set(&stm_gpiob, 3, STM_AFR_AF0);
- stm_afr_set(&stm_gpiob, 4, STM_AFR_AF0);
- stm_afr_set(&stm_gpiob, 5, STM_AFR_AF0);
- break;
- }
+ switch (spi_index) {
+ case AO_SPI_1_PA5_PA6_PA7:
+ stm_afr_set(&stm_gpioa, 5, STM_AFR_AF0);
+ stm_afr_set(&stm_gpioa, 6, STM_AFR_AF0);
+ stm_afr_set(&stm_gpioa, 7, STM_AFR_AF0);
break;
- case STM_SPI_INDEX(2):
- switch (spi_index) {
- case AO_SPI_2_PB13_PB14_PB15:
- stm_afr_set(&stm_gpiob, 13, STM_AFR_AF0);
- stm_afr_set(&stm_gpiob, 14, STM_AFR_AF0);
- stm_afr_set(&stm_gpiob, 15, STM_AFR_AF0);
- break;
- }
+ case AO_SPI_1_PB3_PB4_PB5:
+ stm_afr_set(&stm_gpiob, 3, STM_AFR_AF0);
+ stm_afr_set(&stm_gpiob, 4, STM_AFR_AF0);
+ stm_afr_set(&stm_gpiob, 5, STM_AFR_AF0);
+ break;
+ case AO_SPI_2_PB13_PB14_PB15:
+ stm_afr_set(&stm_gpiob, 13, STM_AFR_AF0);
+ stm_afr_set(&stm_gpiob, 14, STM_AFR_AF0);
+ stm_afr_set(&stm_gpiob, 15, STM_AFR_AF0);
break;
}
}
@@ -369,6 +412,20 @@ ao_spi_config(uint8_t spi_index, uint32_t speed)
uint8_t id = AO_SPI_INDEX(spi_index);
struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
+ if (spi_index != ao_spi_index[id]) {
+
+ /* Disable old config
+ */
+ ao_spi_disable_index(ao_spi_index[id]);
+
+ /* Enable new config
+ */
+ ao_spi_enable_index(spi_index);
+
+ /* Remember current config
+ */
+ ao_spi_index[id] = spi_index;
+ }
stm_spi->cr2 = SPI_CR2;
stm_spi->cr1 = ((0 << STM_SPI_CR1_BIDIMODE) | /* Three wire mode */
(0 << STM_SPI_CR1_BIDIOE) |
@@ -384,21 +441,6 @@ ao_spi_config(uint8_t spi_index, uint32_t speed)
(1 << STM_SPI_CR1_MSTR) |
(0 << STM_SPI_CR1_CPOL) | /* Format 0 */
(0 << STM_SPI_CR1_CPHA));
-
- if (spi_index != ao_spi_index[id]) {
-
- /* Disable old config
- */
- ao_spi_disable_index(ao_spi_index[id]);
-
- /* Enable new config
- */
- ao_spi_enable_index(spi_index);
-
- /* Remember current config
- */
- ao_spi_index[id] = spi_index;
- }
}
uint8_t
@@ -439,10 +481,57 @@ ao_spi_channel_init(uint8_t spi_index)
ao_spi_disable_index(spi_index);
stm_spi->cr1 = 0;
- (void) stm_spi->sr;
stm_spi->cr2 = SPI_CR2_SYNC;
+
+ /* Clear any pending data and error flags */
+ (void) stm_spi->dr;
+ (void) stm_spi->sr;
}
+#if DEBUG
+void
+ao_spi_dump_cmd(void)
+{
+ int s;
+
+ for (s = 0; s < 64; s++) {
+ int i = (spi_task_index + s) & 63;
+ if (spi_tasks[i].which) {
+ int t;
+ const char *name = "(none)";
+ for (t = 0; t < ao_num_tasks; t++)
+ if (ao_tasks[t]->task_id == spi_tasks[i].task) {
+ name = ao_tasks[t]->name;
+ break;
+ }
+ printf("%2d: %5d task %2d which %2d len %5d %s\n",
+ s,
+ spi_tasks[i].tick,
+ spi_tasks[i].task,
+ spi_tasks[i].which,
+ spi_tasks[i].len,
+ name);
+ }
+ }
+ for (s = 0; s < STM_NUM_SPI; s++) {
+ struct stm_spi *spi = ao_spi_stm_info[s].stm_spi;
+
+ printf("%1d: mutex %2d index %3d miso dma %3d mosi dma %3d",
+ s, ao_spi_mutex[s], ao_spi_index[s],
+ ao_spi_stm_info[s].miso_dma_index,
+ ao_spi_stm_info[s].mosi_dma_index);
+ printf(" cr1 %04x cr2 %02x sr %03x\n",
+ spi->cr1, spi->cr2, spi->sr);
+ }
+
+}
+
+static const struct ao_cmds ao_spi_cmds[] = {
+ { ao_spi_dump_cmd, "S\0Dump SPI status" },
+ { 0, NULL }
+};
+#endif
+
void
ao_spi_init(void)
{
@@ -475,4 +564,7 @@ ao_spi_init(void)
ao_spi_index[1] = AO_SPI_CONFIG_NONE;
ao_spi_channel_init(STM_SPI_INDEX(2));
#endif
+#if DEBUG
+ ao_cmd_register(&ao_spi_cmds[0]);
+#endif
}
diff --git a/src/stmf0/ao_timer.c b/src/stmf0/ao_timer.c
index e5bf04a3..5c05e4f1 100644
--- a/src/stmf0/ao_timer.c
+++ b/src/stmf0/ao_timer.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -175,13 +176,12 @@ ao_clock_normal_start(void)
while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
asm("nop");
-#ifdef STM_PLLSRC
/* Disable the PLL */
stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
asm("nop");
- /* PLLVCO to 48MHz (for USB) -> PLLMUL = 3 */
+ /* Set multiplier */
cfgr = stm_rcc.cfgr;
cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
@@ -191,8 +191,8 @@ ao_clock_normal_start(void)
cfgr |= (STM_RCC_CFGR_PLLSRC_TARGET_CLOCK << STM_RCC_CFGR_PLLSRC);
stm_rcc.cfgr = cfgr;
- /* Disable pre divider */
- stm_rcc.cfgr2 = (STM_RCC_CFGR2_PREDIV_1 << STM_RCC_CFGR2_PREDIV);
+ /* Set pre divider */
+ stm_rcc.cfgr2 = (AO_RCC_CFGR2_PLLDIV << STM_RCC_CFGR2_PREDIV);
/* Enable the PLL and wait for it */
stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
@@ -201,9 +201,6 @@ ao_clock_normal_start(void)
#endif
-#endif
-
-
#if AO_HSI48
#define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_HSI48
#define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_HSI48
@@ -225,6 +222,8 @@ ao_clock_normal_start(void)
#define STM_PLLSRC STM_HSI
#define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK 0
#endif
+
+
}
static void
@@ -302,14 +301,34 @@ ao_clock_init(void)
/* Clear reset flags */
stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
+#ifdef AO_MCO_PORT
+ cfgr = stm_rcc.cfgr;
+
+ /* Send PLL clock to MCO */
+ cfgr &= ~(STM_RCC_CFGR_MCO_MASK << STM_RCC_CFGR_MCO);
+ cfgr |= (STM_RCC_CFGR_MCO_PLLCLK << STM_RCC_CFGR_MCO);
+
+ /* Divide by 1 */
+ cfgr &= ~(STM_RCC_CFGR_MCOPRE_DIV_MASK << STM_RCC_CFGR_MCOPRE);
+ cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
+
+ /* Don't divide PLL */
+ cfgr |= (1 << STM_RCC_CFGR_PLL_NODIV);
+
+ stm_rcc.cfgr = cfgr;
+
+ ao_enable_port(AO_MCO_PORT);
+ stm_ospeedr_set(AO_MCO_PORT, AO_MCO_PIN, STM_OSPEEDR_HIGH);
+ stm_afr_set(AO_MCO_PORT, AO_MCO_PIN, AO_MCO_AF);
+#endif
+
#if DEBUG_THE_CLOCK
/* Output SYSCLK on PA8 for measurments */
stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
- stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
- stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
+ stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_HIGH);
stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);
diff --git a/src/stmf0/ao_usb_stm.c b/src/stmf0/ao_usb_stm.c
index fb3d8c85..cbedb996 100644
--- a/src/stmf0/ao_usb_stm.c
+++ b/src/stmf0/ao_usb_stm.c
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/stmf0/stm32f0.h b/src/stmf0/stm32f0.h
index 33eb9c88..054200e0 100644
--- a/src/stmf0/stm32f0.h
+++ b/src/stmf0/stm32f0.h
@@ -3,7 +3,8 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -312,6 +313,15 @@ extern struct stm_rcc stm_rcc;
#define STM_RCC_CFGR_MCO (24)
# define STM_RCC_CFGR_MCO_DISABLE 0
+# define STM_RCC_CFGR_MCO_RC 1
+# define STM_RCC_CFGR_MCO_LSI 2
+# define STM_RCC_CFGR_MCO_LSE 3
+# define STM_RCC_CFGR_MCO_SYSCLK 4
+# define STM_RCC_CFGR_MCO_HSI 5
+# define STM_RCC_CFGR_MCO_HSE 6
+# define STM_RCC_CFGR_MCO_PLLCLK 7
+# define STM_RCC_CFGR_MCO_HSI48 8
+# define STM_RCC_CFGR_MCO_MASK (0xf)
#define STM_RCC_CFGR_PLLMUL (18)
#define STM_RCC_CFGR_PLLMUL_2 0
@@ -1344,6 +1354,290 @@ extern struct stm_i2c stm_i2c1, stm_i2c2;
#define STM_I2C_CCR_CCR 0
#define STM_I2C_CCR_MASK 0x7ff
+struct stm_tim1 {
+ vuint32_t cr1;
+ vuint32_t cr2;
+ vuint32_t smcr;
+ vuint32_t dier;
+
+ vuint32_t sr;
+ vuint32_t egr;
+ vuint32_t ccmr1;
+ vuint32_t ccmr2;
+
+ vuint32_t ccer;
+ vuint32_t cnt;
+ vuint32_t psc;
+ vuint32_t arr;
+
+ vuint32_t rcr;
+ vuint32_t ccr1;
+ vuint32_t ccr2;
+ vuint32_t ccr3;
+
+ vuint32_t ccr4;
+ vuint32_t bdtr;
+ vuint32_t dcr;
+ vuint32_t dmar;
+};
+
+#define STM_TIM1_CR1_CKD 8
+#define STM_TIM1_CR1_CKD_1 0
+#define STM_TIM1_CR1_CKD_2 1
+#define STM_TIM1_CR1_CKD_4 2
+
+#define STM_TIM1_CR1_ARPE 7
+
+#define STM_TIM1_CR1_CMS 5
+#define STM_TIM1_CR1_CMS_EDGE 0
+#define STM_TIM1_CR1_CMS_CENTER_1 1
+#define STM_TIM1_CR1_CMS_CENTER_2 2
+#define STM_TIM1_CR1_CMS_CENTER_3 3
+
+#define STM_TIM1_CR1_DIR 4
+#define STM_TIM1_CR1_DIR_UP 0
+#define STM_TIM1_CR1_DIR_DOWn 1
+#define STM_TIM1_CR1_OPM 3
+#define STM_TIM1_CR1_URS 2
+#define STM_TIM1_CR1_UDIS 1
+#define STM_TIM1_CR1_CEN 0
+
+#define STM_TIM1_CR2_OIS4 14
+#define STM_TIM1_CR2_OIS3N 13
+#define STM_TIM1_CR2_OIS3 12
+#define STM_TIM1_CR2_OIS2N 11
+#define STM_TIM1_CR2_OIS2 10
+#define STM_TIM1_CR2_OIS1N 9
+#define STM_TIM1_CR2_OSI1 8
+#define STM_TIM1_CR2_TI1S 7
+#define STM_TIM1_CR2_MMS 4
+#define STM_TIM1_CR2_MMS_RESET 0
+#define STM_TIM1_CR2_MMS_ENABLE 1
+#define STM_TIM1_CR2_MMS_UPDATE 2
+#define STM_TIM1_CR2_MMS_COMPARE_PULSE 3
+#define STM_TIM1_CR2_MMS_COMPARE_OC1REF 4
+#define STM_TIM1_CR2_MMS_COMPARE_OC2REF 5
+#define STM_TIM1_CR2_MMS_COMPARE_OC3REF 6
+#define STM_TIM1_CR2_MMS_COMPARE_OC4REF 7
+#define STM_TIM1_CR2_CCDS 3
+#define STM_TIM1_CR2_CCUS 2
+#define STM_TIM1_CR2_CCPC 0
+
+#define STM_TIM1_SMCR_ETP 15
+#define STM_TIM1_SMCR_ECE 14
+#define STM_TIM1_SMCR_ETPS 12
+#define STM_TIM1_SMCR_ETPS_OFF 0
+#define STM_TIM1_SMCR_ETPS_DIV_2 1
+#define STM_TIM1_SMCR_ETPS_DIV_4 2
+#define STM_TIM1_SMCR_ETPS_DIV_8 3
+
+#define STM_TIM1_SMCR_ETF 8
+#define STM_TIM1_SMCR_ETF_NONE 0
+#define STM_TIM1_SMCR_ETF_DIV_1_N_2 1
+#define STM_TIM1_SMCR_ETF_DIV_1_N_4 2
+#define STM_TIM1_SMCR_ETF_DIV_1_N_8 3
+#define STM_TIM1_SMCR_ETF_DIV_2_N_6 4
+#define STM_TIM1_SMCR_ETF_DIV_2_N_8 5
+#define STM_TIM1_SMCR_ETF_DIV_4_N_6 6
+#define STM_TIM1_SMCR_ETF_DIV_4_N_8 7
+#define STM_TIM1_SMCR_ETF_DIV_8_N_6 8
+#define STM_TIM1_SMCR_ETF_DIV_8_N_8 9
+#define STM_TIM1_SMCR_ETF_DIV_16_N_5 10
+#define STM_TIM1_SMCR_ETF_DIV_16_N_6 11
+#define STM_TIM1_SMCR_ETF_DIV_16_N_8 12
+#define STM_TIM1_SMCR_ETF_DIV_32_N_5 13
+#define STM_TIM1_SMCR_ETF_DIV_32_N_6 14
+#define STM_TIM1_SMCR_ETF_DIV_32_N_8 15
+
+#define STM_TIM1_SMCR_MSM 7
+#define STM_TIM1_SMCR_TS 4
+#define STM_TIM1_SMCR_TS_ITR0 0
+#define STM_TIM1_SMCR_TS_ITR1 1
+#define STM_TIM1_SMCR_TS_ITR2 2
+#define STM_TIM1_SMCR_TS_ITR3 3
+#define STM_TIM1_SMCR_TS_TI1F_ED 4
+#define STM_TIM1_SMCR_TS_TI1FP1 5
+#define STM_TIM1_SMCR_TS_TI2FP2 6
+#define STM_TIM1_SMCR_TS_ETRF 7
+
+#define STM_TIM1_SMCR_OCCS 3
+#define STM_TIM1_SMCR_SMS 0
+#define STM_TIM1_SMCR_SMS_DISABLE 0
+#define STM_TIM1_SMCR_SMS_ENCODER_1 1
+#define STM_TIM1_SMCR_SMS_ENCODER_2 2
+#define STM_TIM1_SMCR_SMS_ENCODER_3 3
+#define STM_TIM1_SMCR_SMS_RESET 4
+#define STM_TIM1_SMCR_SMS_GATED 5
+#define STM_TIM1_SMCR_SMS_TRIGGER 6
+#define STM_TIM1_SMCR_SMS_EXTERNAL 7
+
+#define STM_TIM1_DIER_TDE 14
+#define STM_TIM1_DIER_COMDE 13
+#define STM_TIM1_DIER_CC4DE 12
+#define STM_TIM1_DIER_CC3DE 11
+#define STM_TIM1_DIER_CC2DE 10
+#define STM_TIM1_DIER_CC1DE 9
+#define STM_TIM1_DIER_UDE 8
+#define STM_TIM1_DIER_BIE 7
+#define STM_TIM1_DIER_TIE 6
+#define STM_TIM1_DIER_COMIE 5
+#define STM_TIM1_DIER_CC4IE 4
+#define STM_TIM1_DIER_CC3IE 3
+#define STM_TIM1_DIER_CC2IE 2
+#define STM_TIM1_DIER_CC1IE 1
+#define STM_TIM1_DIER_UIE 0
+
+#define STM_TIM1_SR_CC4OF 12
+#define STM_TIM1_SR_CC3OF 11
+#define STM_TIM1_SR_CC2OF 10
+#define STM_TIM1_SR_CC1OF 9
+#define STM_TIM1_SR_BIF 7
+#define STM_TIM1_SR_TIF 6
+#define STM_TIM1_SR_COMIF 5
+#define STM_TIM1_SR_CC4IF 4
+#define STM_TIM1_SR_CC3IF 3
+#define STM_TIM1_SR_CC2IF 2
+#define STM_TIM1_SR_CC1IF 1
+#define STM_TIM1_SR_UIF 0
+
+#define STM_TIM1_EGR_BG 7
+#define STM_TIM1_EGR_TG 6
+#define STM_TIM1_EGR_COMG 5
+#define STM_TIM1_EGR_CC4G 4
+#define STM_TIM1_EGR_CC3G 3
+#define STM_TIM1_EGR_CC2G 2
+#define STM_TIM1_EGR_CC1G 1
+#define STM_TIM1_EGR_UG 0
+
+#define STM_TIM1_CCMR1_OC2CE 15
+#define STM_TIM1_CCMR1_OC2M 12
+#define STM_TIM1_CCMR1_OC2PE 11
+#define STM_TIM1_CCMR1_OC2FE 10
+#define STM_TIM1_CCMR1_CC2S 8
+#define STM_TIM1_CCMR1_OC1CE 7
+#define STM_TIM1_CCMR1_OC1M 4
+#define STM_TIM1_CCMR_OCM_FROZEN 0
+#define STM_TIM1_CCMR_OCM_1_HIGH_MATCH 1
+#define STM_TIM1_CCMR_OCM_1_LOW_MATCH 2
+#define STM_TIM1_CCMR_OCM_TOGGLE 3
+#define STM_TIM1_CCMR_OCM_FORCE_LOW 4
+#define STM_TIM1_CCMR_OCM_FORCE_HIGH 5
+#define STM_TIM1_CCMR_OCM_PWM_MODE_1 6
+#define STM_TIM1_CCMR_OCM_PWM_MODE_2 7
+
+#define STM_TIM1_CCMR1_OC1PE 3
+#define STM_TIM1_CCMR1_OC1FE 2
+#define STM_TIM1_CCMR1_CC1S 0
+#define STM_TIM1_CCMR_CCS_OUTPUT 0
+#define STM_TIM1_CCMR_CCS_INPUT_TI1 1
+#define STM_TIM1_CCMR_CCS_INPUT_TI2 2
+#define STM_TIM1_CCMR_CCS_INPUT_TRC 3
+
+#define STM_TIM1_CCMR1_IC2F 12
+#define STM_TIM1_CCMR1_IC2PSC 10
+#define STM_TIM1_CCMR1_CC2S 8
+#define STM_TIM1_CCMR1_IC1F 4
+#define STM_TIM1_CCMR1_IC1F_NONE 0
+#define STM_TIM1_CCMR1_IC1F_DIV_1_N_2 1
+#define STM_TIM1_CCMR1_IC1F_DIV_1_N_4 2
+#define STM_TIM1_CCMR1_IC1F_DIV_1_N_8 3
+#define STM_TIM1_CCMR1_IC1F_DIV_2_N_6 4
+#define STM_TIM1_CCMR1_IC1F_DIV_2_N_8 5
+#define STM_TIM1_CCMR1_IC1F_DIV_4_N_6 6
+#define STM_TIM1_CCMR1_IC1F_DIV_4_N_8 7
+#define STM_TIM1_CCMR1_IC1F_DIV_8_N_6 8
+#define STM_TIM1_CCMR1_IC1F_DIV_8_N_8 9
+#define STM_TIM1_CCMR1_IC1F_DIV_16_N_5 10
+#define STM_TIM1_CCMR1_IC1F_DIV_16_N_6 11
+#define STM_TIM1_CCMR1_IC1F_DIV_16_N_8 12
+#define STM_TIM1_CCMR1_IC1F_DIV_32_N_5 13
+#define STM_TIM1_CCMR1_IC1F_DIV_32_N_6 14
+#define STM_TIM1_CCMR1_IC1F_DIV_32_N_8 15
+
+#define STM_TIM1_CCMR1_IC1PSC 2
+#define STM_TIM1_CCMR1_IC1PSC_NONE 0
+#define STM_TIM1_CCMR1_IC1PSC_2 1
+#define STM_TIM1_CCMR1_IC1PSC_4 2
+#define STM_TIM1_CCMR1_IC1PSC_8 3
+
+#define STM_TIM1_CCMR1_CC1S 0
+#define STM_TIM1_CCMR1_CC1S_OUTPUT 0
+#define STM_TIM1_CCMR1_CC1S_TI1 1
+#define STM_TIM1_CCMR1_CC1S_TI2 2
+#define STM_TIM1_CCMR1_CC1S_TRC 3
+
+#define STM_TIM1_CCMR2_OC4CE 15
+#define STM_TIM1_CCMR2_OC4M 12
+#define STM_TIM1_CCMR2_OC4PE 11
+#define STM_TIM1_CCMR2_OC4FE 10
+#define STM_TIM1_CCMR2_CC4S 8
+#define STM_TIM1_CCMR2_CCS_OUTPUT 0
+#define STM_TIM1_CCMR2_CCS_INPUT_TI3 1
+#define STM_TIM1_CCMR2_CCS_INPUT_TI4 2
+#define STM_TIM1_CCMR2_CCS_INPUT_TRC 3
+#define STM_TIM1_CCMR2_OC3CE 7
+#define STM_TIM1_CCMR2_OC3M 4
+#define STM_TIM1_CCMR2_OC3PE 3
+#define STM_TIM1_CCMR2_OC3FE 2
+#define STM_TIM1_CCMR2_CC3S 0
+
+#define STM_TIM1_CCMR2_IC4F 12
+#define STM_TIM1_CCMR2_IC2PSC 10
+#define STM_TIM1_CCMR2_CC4S 8
+#define STM_TIM1_CCMR2_IC3F 4
+#define STM_TIM1_CCMR2_IC1F_NONE 0
+#define STM_TIM1_CCMR2_IC1F_DIV_1_N_2 1
+#define STM_TIM1_CCMR2_IC1F_DIV_1_N_4 2
+#define STM_TIM1_CCMR2_IC1F_DIV_1_N_8 3
+#define STM_TIM1_CCMR2_IC1F_DIV_2_N_6 4
+#define STM_TIM1_CCMR2_IC1F_DIV_2_N_8 5
+#define STM_TIM1_CCMR2_IC1F_DIV_4_N_6 6
+#define STM_TIM1_CCMR2_IC1F_DIV_4_N_8 7
+#define STM_TIM1_CCMR2_IC1F_DIV_8_N_6 8
+#define STM_TIM1_CCMR2_IC1F_DIV_8_N_8 9
+#define STM_TIM1_CCMR2_IC1F_DIV_16_N_5 10
+#define STM_TIM1_CCMR2_IC1F_DIV_16_N_6 11
+#define STM_TIM1_CCMR2_IC1F_DIV_16_N_8 12
+#define STM_TIM1_CCMR2_IC1F_DIV_32_N_5 13
+#define STM_TIM1_CCMR2_IC1F_DIV_32_N_6 14
+#define STM_TIM1_CCMR2_IC1F_DIV_32_N_8 15
+
+#define STM_TIM1_CCER_CC4P 13
+#define STM_TIM1_CCER_CC4E 12
+#define STM_TIM1_CCER_CC3NP 11
+#define STM_TIM1_CCER_CC3NE 10
+#define STM_TIM1_CCER_CC3P 9
+#define STM_TIM1_CCER_CC3E 8
+#define STM_TIM1_CCER_CC2NP 7
+#define STM_TIM1_CCER_CC2NE 6
+#define STM_TIM1_CCER_CC2P 5
+#define STM_TIM1_CCER_CC2E 4
+#define STM_TIM1_CCER_CC1BP 3
+#define STM_TIM1_CCER_CC1NE 2
+#define STM_TIM1_CCER_CC1P 1
+#define STM_TIM1_CCER_CC1E 0
+
+#define STM_TIM1_BDTR_MOE 15
+#define STM_TIM1_BDTR_AOE 14
+#define STM_TIM1_BDTR_BKP 13
+#define STM_TIM1_BDTR_BKE 12
+#define STM_TIM1_BDTR_OSSR 11
+#define STM_TIM1_BDTR_OSSI 10
+#define STM_TIM1_BDTR_LOCK 8
+#define STM_TIM1_BDTR_LOCK_OFF 0
+#define STM_TIM1_BDTR_LOCK_LEVEL_1 1
+#define STM_TIM1_BDTR_LOCK_LEVEL_2 2
+#define STM_TIM1_BDTR_LOCK_LEVEL_3 3
+
+#define STM_TIM1_BDTR_DTG 0
+
+#define STM_TIM1_DCR_DBL 8
+#define STM_TIM1_DCR_DBA 0
+
+extern struct stm_tim1 stm_tim1;
+
+#define stm_tim1 (*(struct stm_tim1 *)0x40012c00)
+
struct stm_tim23 {
vuint32_t cr1;
vuint32_t cr2;
@@ -1518,15 +1812,15 @@ extern struct stm_tim23 stm_tim2, stm_tim3;
#define STM_TIM23_CCMR2_OC4CE 15
#define STM_TIM23_CCMR2_OC4M 12
-#define STM_TIM23_CCMR2_OC4M_FROZEN 0
-#define STM_TIM23_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
-#define STM_TIM23_CCMR2_OC4M_SET_LOW_ON_MATCH 2
-#define STM_TIM23_CCMR2_OC4M_TOGGLE 3
-#define STM_TIM23_CCMR2_OC4M_FORCE_LOW 4
-#define STM_TIM23_CCMR2_OC4M_FORCE_HIGH 5
-#define STM_TIM23_CCMR2_OC4M_PWM_MODE_1 6
-#define STM_TIM23_CCMR2_OC4M_PWM_MODE_2 7
-#define STM_TIM23_CCMR2_OC4M_MASK 7
+#define STM_TIM23_CCMR2_OCM_FROZEN 0
+#define STM_TIM23_CCMR2_OCM_SET_HIGH_ON_MATCH 1
+#define STM_TIM23_CCMR2_OCM_SET_LOW_ON_MATCH 2
+#define STM_TIM23_CCMR2_OCM_TOGGLE 3
+#define STM_TIM23_CCMR2_OCM_FORCE_LOW 4
+#define STM_TIM23_CCMR2_OCM_FORCE_HIGH 5
+#define STM_TIM23_CCMR2_OCM_PWM_MODE_1 6
+#define STM_TIM23_CCMR2_OCM_PWM_MODE_2 7
+#define STM_TIM23_CCMR2_OCM_MASK 7
#define STM_TIM23_CCMR2_OC4PE 11
#define STM_TIM23_CCMR2_OC4FE 10
#define STM_TIM23_CCMR2_CC4S 8
@@ -1538,15 +1832,15 @@ extern struct stm_tim23 stm_tim2, stm_tim3;
#define STM_TIM23_CCMR2_OC3CE 7
#define STM_TIM23_CCMR2_OC3M 4
-#define STM_TIM23_CCMR2_OC3M_FROZEN 0
-#define STM_TIM23_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
-#define STM_TIM23_CCMR2_OC3M_SET_LOW_ON_MATCH 2
-#define STM_TIM23_CCMR2_OC3M_TOGGLE 3
-#define STM_TIM23_CCMR2_OC3M_FORCE_LOW 4
-#define STM_TIM23_CCMR2_OC3M_FORCE_HIGH 5
+#define STM_TIM23_CCMR2_OCM_FROZEN 0
+#define STM_TIM23_CCMR2_OCM_SET_HIGH_ON_MATCH 1
+#define STM_TIM23_CCMR2_OCM_SET_LOW_ON_MATCH 2
+#define STM_TIM23_CCMR2_OCM_TOGGLE 3
+#define STM_TIM23_CCMR2_OCM_FORCE_LOW 4
+#define STM_TIM23_CCMR2_OCM_FORCE_HIGH 5
#define STM_TIM23_CCMR2_OC3M_PWM_MODE_1 6
-#define STM_TIM23_CCMR2_OC3M_PWM_MODE_2 7
-#define STM_TIM23_CCMR2_OC3M_MASK 7
+#define STM_TIM23_CCMR2_OCM_PWM_MODE_2 7
+#define STM_TIM23_CCMR2_OCM_MASK 7
#define STM_TIM23_CCMR2_OC3PE 11
#define STM_TIM23_CCMR2_OC3FE 2
#define STM_TIM23_CCMR2_CC3S 0
generated by cgit v1.2.3 (git 2.39.1) at 2025-10-17 17:00:15 +0000