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-rw-r--r--src/stm/Makefile-flash.defs2
-rw-r--r--src/stm/ao_arch.h2
-rw-r--r--src/stm/ao_arch_funcs.h15
-rw-r--r--src/stm/ao_beep_stm.c48
-rw-r--r--src/stm/ao_timer.c25
-rw-r--r--src/stm/stm32l.h2
6 files changed, 68 insertions, 26 deletions
diff --git a/src/stm/Makefile-flash.defs b/src/stm/Makefile-flash.defs
index 016bb7e7..86f76d46 100644
--- a/src/stm/Makefile-flash.defs
+++ b/src/stm/Makefile-flash.defs
@@ -6,7 +6,7 @@ vpath ao-make-product.5c $(TOPDIR)/util
.elf.ihx:
objcopy -O ihex $*.elf $@
-CC=arm-none-eabi-gcc
+CC=/opt/cortex/bin/arm-none-eabi-gcc
SAT=/opt/cortex
SAT_CLIB=$(SAT)/lib/pdclib-cortex-m3.a
SAT_CFLAGS=-I$(SAT)/include
diff --git a/src/stm/ao_arch.h b/src/stm/ao_arch.h
index adc288c3..42fe727a 100644
--- a/src/stm/ao_arch.h
+++ b/src/stm/ao_arch.h
@@ -34,6 +34,8 @@
#define AO_TICK_SIGNED int16_t
#endif
+#define AO_PORT_TYPE uint16_t
+
/* Various definitions to make GCC look more like SDCC */
#define ao_arch_naked_declare __attribute__((naked))
diff --git a/src/stm/ao_arch_funcs.h b/src/stm/ao_arch_funcs.h
index 6fe86e62..9bb2d7cd 100644
--- a/src/stm/ao_arch_funcs.h
+++ b/src/stm/ao_arch_funcs.h
@@ -338,6 +338,11 @@ static inline void ao_arch_restore_stack(void) {
asm("bx lr");
}
+#ifndef HAS_SAMPLE_PROFILE
+#define HAS_SAMPLE_PROFILE 0
+#endif
+
+#if !HAS_SAMPLE_PROFILE
#define HAS_ARCH_START_SCHEDULER 1
static inline void ao_arch_start_scheduler(void) {
@@ -350,15 +355,17 @@ static inline void ao_arch_start_scheduler(void) {
control |= (1 << 1);
asm("msr control,%0" : : "r" (control));
}
+#endif
#define ao_arch_isr_stack()
#endif
-#define ao_arch_wait_interrupt() do { \
- asm(".global ao_idle_loc\n\twfi\nao_idle_loc:"); \
- ao_arch_release_interrupts(); \
- ao_arch_block_interrupts(); \
+#define ao_arch_wait_interrupt() do { \
+ asm("\twfi\n"); \
+ ao_arch_release_interrupts(); \
+ asm(".global ao_idle_loc\nao_idle_loc:"); \
+ ao_arch_block_interrupts(); \
} while (0)
#define ao_arch_critical(b) do { \
diff --git a/src/stm/ao_beep_stm.c b/src/stm/ao_beep_stm.c
index 4761fbfc..a95d869b 100644
--- a/src/stm/ao_beep_stm.c
+++ b/src/stm/ao_beep_stm.c
@@ -17,6 +17,10 @@
#include "ao.h"
+#ifndef BEEPER_CHANNEL
+#define BEEPER_CHANNEL 1
+#endif
+
void
ao_beep(uint8_t beep)
{
@@ -56,6 +60,7 @@ ao_beep(uint8_t beep)
* is enabled and active high.
*/
+#if BEEPER_CHANNEL == 1
stm_tim3.ccmr1 = ((0 << STM_TIM234_CCMR1_OC2CE) |
(STM_TIM234_CCMR1_OC2M_FROZEN << STM_TIM234_CCMR1_OC2M) |
(0 << STM_TIM234_CCMR1_OC2PE) |
@@ -68,7 +73,6 @@ ao_beep(uint8_t beep)
(0 << STM_TIM234_CCMR1_OC1FE) |
(STM_TIM234_CCMR1_CC1S_OUTPUT << STM_TIM234_CCMR1_CC1S));
-
stm_tim3.ccer = ((0 << STM_TIM234_CCER_CC4NP) |
(0 << STM_TIM234_CCER_CC4P) |
(0 << STM_TIM234_CCER_CC4E) |
@@ -81,6 +85,33 @@ ao_beep(uint8_t beep)
(0 << STM_TIM234_CCER_CC1NP) |
(0 << STM_TIM234_CCER_CC1P) |
(1 << STM_TIM234_CCER_CC1E));
+#endif
+#if BEEPER_CHANNEL == 4
+ stm_tim3.ccmr2 = ((0 << STM_TIM234_CCMR2_OC4CE) |
+ (STM_TIM234_CCMR2_OC4M_TOGGLE << STM_TIM234_CCMR2_OC4M) |
+ (0 << STM_TIM234_CCMR2_OC4PE) |
+ (0 << STM_TIM234_CCMR2_OC4FE) |
+ (STM_TIM234_CCMR2_CC4S_OUTPUT << STM_TIM234_CCMR2_CC4S) |
+
+ (0 << STM_TIM234_CCMR2_OC3CE) |
+ (STM_TIM234_CCMR2_OC3M_FROZEN << STM_TIM234_CCMR2_OC3M) |
+ (0 << STM_TIM234_CCMR2_OC3PE) |
+ (0 << STM_TIM234_CCMR2_OC3FE) |
+ (STM_TIM234_CCMR2_CC3S_OUTPUT << STM_TIM234_CCMR2_CC3S));
+
+ stm_tim3.ccer = ((0 << STM_TIM234_CCER_CC4NP) |
+ (0 << STM_TIM234_CCER_CC4P) |
+ (1 << STM_TIM234_CCER_CC4E) |
+ (0 << STM_TIM234_CCER_CC3NP) |
+ (0 << STM_TIM234_CCER_CC3P) |
+ (0 << STM_TIM234_CCER_CC3E) |
+ (0 << STM_TIM234_CCER_CC2NP) |
+ (0 << STM_TIM234_CCER_CC2P) |
+ (0 << STM_TIM234_CCER_CC2E) |
+ (0 << STM_TIM234_CCER_CC1NP) |
+ (0 << STM_TIM234_CCER_CC1P) |
+ (0 << STM_TIM234_CCER_CC1E));
+#endif
/* 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. */
@@ -110,13 +141,22 @@ ao_beep_for(uint8_t beep, uint16_t ticks) __reentrant
void
ao_beep_init(void)
{
- /* Our beeper is on PC6, which is hooked to TIM3_CH1,
- * which is on PC6
- */
+#if BEEPER_CHANNEL == 1
+ /* Our beeper is on PC6, which is hooked to TIM3_CH1.
+ */
stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN);
stm_afr_set(&stm_gpioc, 6, STM_AFR_AF2);
+#endif
+#if BEEPER_CHANNEL == 4
+
+ /* Our beeper is on PB1, which is hooked to TIM3_CH4.
+ */
+ stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
+
+ stm_afr_set(&stm_gpiob, 1, STM_AFR_AF2);
+#endif
/* Leave the timer off until requested */
diff --git a/src/stm/ao_timer.c b/src/stm/ao_timer.c
index daf2f400..34f9edb9 100644
--- a/src/stm/ao_timer.c
+++ b/src/stm/ao_timer.c
@@ -67,20 +67,6 @@ ao_timer_set_adc_interval(uint8_t interval)
}
#endif
-/*
- * According to the STM clock-configuration, timers run
- * twice as fast as the APB1 clock *if* the APB1 prescaler
- * is greater than 1.
- */
-
-#if AO_APB1_PRESCALER > 1
-#define TIMER_23467_SCALER 2
-#else
-#define TIMER_23467_SCALER 1
-#endif
-
-#define TIMER_10kHz ((AO_PCLK1 * TIMER_23467_SCALER) / 10000)
-
#define SYSTICK_RELOAD (AO_SYSTICK / 100 - 1)
void
@@ -104,7 +90,15 @@ ao_clock_init(void)
/* Switch to MSI while messing about */
stm_rcc.cr |= (1 << STM_RCC_CR_MSION);
while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY)))
- asm("nop");
+ ao_arch_nop();
+
+ stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
+ (STM_RCC_CFGR_SW_MSI << STM_RCC_CFGR_SW);
+
+ /* wait for system to switch to MSI */
+ while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
+ (STM_RCC_CFGR_SWS_MSI << STM_RCC_CFGR_SWS))
+ ao_arch_nop();
/* reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE */
stm_rcc.cfgr &= (uint32_t)0x88FFC00C;
@@ -155,7 +149,6 @@ ao_clock_init(void)
stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
/* Enable 1 wait state so the CPU can run at 32MHz */
- /* (haven't managed to run the CPU at 32MHz yet, it's at 16MHz) */
stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
/* Enable power interface clock */
diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h
index 1868468f..ff3f5336 100644
--- a/src/stm/stm32l.h
+++ b/src/stm/stm32l.h
@@ -1739,7 +1739,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
#define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3
#define STM_TIM234_CCMR1_CC1S_MASK 3
-#define STM_TIM234_CCMR2_OC2CE 15
+#define STM_TIM234_CCMR2_OC4CE 15
#define STM_TIM234_CCMR2_OC4M 12
#define STM_TIM234_CCMR2_OC4M_FROZEN 0
#define STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
generated by cgit v1.2.3 (git 2.39.1) at 2025-10-17 11:34:38 +0000