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-rw-r--r--src/stm/ao_arch.h2
-rw-r--r--src/stm/ao_sample_profile_timer.c115
-rw-r--r--src/stm/ao_sample_profile_timer.h32
-rw-r--r--src/stm/stm32l.h134
4 files changed, 280 insertions, 3 deletions
diff --git a/src/stm/ao_arch.h b/src/stm/ao_arch.h
index 87eda18b..f2de719c 100644
--- a/src/stm/ao_arch.h
+++ b/src/stm/ao_arch.h
@@ -143,7 +143,7 @@ extern const uint32_t ao_radio_cal;
#define ao_arch_cpu_idle() do { \
- asm("wfi"); \
+ asm(".global ao_idle_loc\n\twfi\nao_idle_loc:"); \
} while (0)
#define ao_arch_restore_stack() do { \
diff --git a/src/stm/ao_sample_profile_timer.c b/src/stm/ao_sample_profile_timer.c
new file mode 100644
index 00000000..d5af3a57
--- /dev/null
+++ b/src/stm/ao_sample_profile_timer.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright © 2012 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#include <ao.h>
+#include <ao_sample_profile.h>
+
+struct stm_exception {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r12;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t psr;
+};
+
+void
+stm_tim10_isr(void)
+{
+ struct stm_exception *ex;
+
+ asm("mov %0,sp" : "=&r" (ex));
+
+ stm_tim10.sr = 0;
+ ao_sample_profile_point(ex->pc, stm_tim11.cnt, (ex->psr & 0xff) != 0);
+}
+
+uint16_t
+ao_sample_profile_timer_start(void)
+{
+ /* Reset counts */
+ stm_tim11.cnt = 0;
+ stm_tim10.cnt = 0;
+
+ /* Turn on timer 11 */
+ stm_tim11.cr1 = ((0 << STM_TIM1011_CR1_CKD) |
+ (0 << STM_TIM1011_CR1_ARPE) |
+ (1 << STM_TIM1011_CR1_URS) |
+ (0 << STM_TIM1011_CR1_UDIS) |
+ (1 << STM_TIM1011_CR1_CEN));
+
+ /* Turn on timer 10 */
+ stm_tim10.cr1 = ((0 << STM_TIM1011_CR1_CKD) |
+ (0 << STM_TIM1011_CR1_ARPE) |
+ (1 << STM_TIM1011_CR1_URS) |
+ (0 << STM_TIM1011_CR1_UDIS) |
+ (1 << STM_TIM1011_CR1_CEN));
+ return stm_tim11.cnt;
+}
+
+void
+ao_sample_profile_timer_stop(void)
+{
+ stm_tim10.cr1 = 0;
+ stm_tim11.cr1 = 0;
+}
+
+#if AO_APB2_PRESCALER > 1
+#define TIMER_91011_SCALER 2
+#else
+#define TIMER_91011_SCALER 1
+#endif
+
+#define TIMER_10kHz ((AO_PCLK2 * TIMER_91011_SCALER) / 10000)
+#define TIMER_1kHz ((AO_PCLK2 * TIMER_91011_SCALER) / 1000)
+
+void
+ao_sample_profile_timer_init(void)
+{
+ /* Turn on power for timer 10 and 11 */
+ stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_TIM10EN) | (1 << STM_RCC_APB2ENR_TIM11EN);
+
+ /* Timer 10 is the 1kHz interrupt */
+ stm_tim10.cr1 = 0;
+ stm_tim10.psc = TIMER_10kHz;
+ stm_tim10.arr = 9;
+ stm_tim10.cnt = 0;
+
+ /* Enable timer 10 update interrupt */
+ stm_tim10.dier = (1 << STM_TIM1011_DIER_UIE);
+
+ /* Poke timer to reload values */
+ stm_tim10.egr |= (1 << STM_TIM1011_EGR_UG);
+
+ /* Timer 11 is the 1kHz counter */
+ stm_tim11.cr1 = 0;
+ stm_tim11.psc = TIMER_1kHz;
+ stm_tim11.arr = 0xffff;
+ stm_tim11.cnt = 0;
+
+ /* Disable interrupts for timer 11 */
+ stm_tim11.dier = 0;
+
+ /* Poke timer to reload values */
+ stm_tim11.egr |= (1 << STM_TIM1011_EGR_UG);
+
+ stm_tim10.sr = 0;
+ stm_nvic_set_enable(STM_ISR_TIM10_POS);
+ stm_nvic_set_priority(STM_ISR_TIM10_POS, AO_STM_NVIC_HIGH_PRIORITY);
+}
diff --git a/src/stm/ao_sample_profile_timer.h b/src/stm/ao_sample_profile_timer.h
new file mode 100644
index 00000000..1da1bfb4
--- /dev/null
+++ b/src/stm/ao_sample_profile_timer.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright © 2012 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#ifndef _AO_SAMPLE_PROFILE_TIMER_H_
+#define _AO_SAMPLE_PROFILE_TIMER_H_
+
+uint16_t
+ao_sample_profile_timer_start(void);
+
+void
+ao_sample_profile_timer_stop(void);
+
+void
+ao_sample_profile_timer_init(void);
+
+#define ao_sample_profile_timer_value() ((uint16_t) stm_tim11.cnt)
+
+#endif /* _AO_SAMPLE_PROFILE_TIMER_H_ */
diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h
index 25f5af07..e950d09b 100644
--- a/src/stm/stm32l.h
+++ b/src/stm/stm32l.h
@@ -254,8 +254,138 @@ struct stm_tim {
};
extern struct stm_tim stm_tim9;
-extern struct stm_tim stm_tim10;
-extern struct stm_tim stm_tim11;
+
+struct stm_tim1011 {
+ vuint32_t cr1;
+ uint32_t unused_4;
+ vuint32_t smcr;
+ vuint32_t dier;
+ vuint32_t sr;
+ vuint32_t egr;
+ vuint32_t ccmr1;
+ uint32_t unused_1c;
+ vuint32_t ccer;
+ vuint32_t cnt;
+ vuint32_t psc;
+ vuint32_t arr;
+ uint32_t unused_30;
+ vuint32_t ccr1;
+ uint32_t unused_38;
+ uint32_t unused_3c;
+ uint32_t unused_40;
+ uint32_t unused_44;
+ uint32_t unused_48;
+ uint32_t unused_4c;
+ vuint32_t or;
+};
+
+extern struct stm_tim1011 stm_tim10;
+extern struct stm_tim1011 stm_tim11;
+
+#define STM_TIM1011_CR1_CKD 8
+#define STM_TIM1011_CR1_CKD_1 0
+#define STM_TIM1011_CR1_CKD_2 1
+#define STM_TIM1011_CR1_CKD_4 2
+#define STM_TIM1011_CR1_CKD_MASK 3
+#define STM_TIM1011_CR1_ARPE 7
+#define STM_TIM1011_CR1_URS 2
+#define STM_TIM1011_CR1_UDIS 1
+#define STM_TIM1011_CR1_CEN 0
+
+#define STM_TIM1011_SMCR_ETP 15
+#define STM_TIM1011_SMCR_ECE 14
+#define STM_TIM1011_SMCR_ETPS 12
+#define STM_TIM1011_SMCR_ETPS_OFF 0
+#define STM_TIM1011_SMCR_ETPS_2 1
+#define STM_TIM1011_SMCR_ETPS_4 2
+#define STM_TIM1011_SMCR_ETPS_8 3
+#define STM_TIM1011_SMCR_ETPS_MASK 3
+#define STM_TIM1011_SMCR_ETF 8
+#define STM_TIM1011_SMCR_ETF_NONE 0
+#define STM_TIM1011_SMCR_ETF_CK_INT_2 1
+#define STM_TIM1011_SMCR_ETF_CK_INT_4 2
+#define STM_TIM1011_SMCR_ETF_CK_INT_8 3
+#define STM_TIM1011_SMCR_ETF_DTS_2_6 4
+#define STM_TIM1011_SMCR_ETF_DTS_2_8 5
+#define STM_TIM1011_SMCR_ETF_DTS_4_6 6
+#define STM_TIM1011_SMCR_ETF_DTS_4_8 7
+#define STM_TIM1011_SMCR_ETF_DTS_8_6 8
+#define STM_TIM1011_SMCR_ETF_DTS_8_8 9
+#define STM_TIM1011_SMCR_ETF_DTS_16_5 10
+#define STM_TIM1011_SMCR_ETF_DTS_16_6 11
+#define STM_TIM1011_SMCR_ETF_DTS_16_8 12
+#define STM_TIM1011_SMCR_ETF_DTS_32_5 13
+#define STM_TIM1011_SMCR_ETF_DTS_32_6 14
+#define STM_TIM1011_SMCR_ETF_DTS_32_8 15
+#define STM_TIM1011_SMCR_ETF_MASK 15
+
+#define STM_TIM1011_DIER_CC1E 1
+#define STM_TIM1011_DIER_UIE 0
+
+#define STM_TIM1011_SR_CC1OF 9
+#define STM_TIM1011_SR_CC1IF 1
+#define STM_TIM1011_SR_UIF 0
+
+#define STM_TIM1011_EGR_CC1G 1
+#define STM_TIM1011_EGR_UG 0
+
+#define STM_TIM1011_CCMR1_OC1CE 7
+#define STM_TIM1011_CCMR1_OC1M 4
+#define STM_TIM1011_CCMR1_OC1M_FROZEN 0
+#define STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH 1
+#define STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
+#define STM_TIM1011_CCMR1_OC1M_TOGGLE 3
+#define STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE 4
+#define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
+#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
+#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
+#define STM_TIM1011_CCMR1_OC1M_MASK 7
+#define STM_TIM1011_CCMR1_OC1PE 3
+#define STM_TIM1011_CCMR1_OC1FE 2
+#define STM_TIM1011_CCMR1_CC1S 0
+#define STM_TIM1011_CCMR1_CC1S_OUTPUT 0
+#define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
+#define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
+#define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
+#define STM_TIM1011_CCMR1_CC1S_MASK 3
+
+#define STM_TIM1011_CCMR1_IC1F_NONE 0
+#define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
+#define STM_TIM1011_CCMR1_IC1F_CK_INT_4 2
+#define STM_TIM1011_CCMR1_IC1F_CK_INT_8 3
+#define STM_TIM1011_CCMR1_IC1F_DTS_2_6 4
+#define STM_TIM1011_CCMR1_IC1F_DTS_2_8 5
+#define STM_TIM1011_CCMR1_IC1F_DTS_4_6 6
+#define STM_TIM1011_CCMR1_IC1F_DTS_4_8 7
+#define STM_TIM1011_CCMR1_IC1F_DTS_8_6 8
+#define STM_TIM1011_CCMR1_IC1F_DTS_8_8 9
+#define STM_TIM1011_CCMR1_IC1F_DTS_16_5 10
+#define STM_TIM1011_CCMR1_IC1F_DTS_16_6 11
+#define STM_TIM1011_CCMR1_IC1F_DTS_16_8 12
+#define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
+#define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
+#define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
+#define STM_TIM1011_CCMR1_IC1F_MASK 15
+#define STM_TIM1011_CCMR1_IC1PSC 2
+#define STM_TIM1011_CCMR1_IC1PSC_1 0
+#define STM_TIM1011_CCMR1_IC1PSC_2 1
+#define STM_TIM1011_CCMR1_IC1PSC_4 2
+#define STM_TIM1011_CCMR1_IC1PSC_8 3
+#define STM_TIM1011_CCMR1_IC1PSC_MASK 3
+#define STM_TIM1011_CCMR1_CC1S 0
+
+#define STM_TIM1011_CCER_CC1NP 3
+#define STM_TIM1011_CCER_CC1P 1
+#define STM_TIM1011_CCER_CC1E 0
+
+#define STM_TIM1011_OR_TI1_RMP_RI 3
+#define STM_TIM1011_ETR_RMP 2
+#define STM_TIM1011_TI1_RMP 0
+#define STM_TIM1011_TI1_RMP_GPIO 0
+#define STM_TIM1011_TI1_RMP_LSI 1
+#define STM_TIM1011_TI1_RMP_LSE 2
+#define STM_TIM1011_TI1_RMP_RTC 3
+#define STM_TIM1011_TI1_RMP_MASK 3
/* Flash interface */
generated by cgit v1.2.3 (git 2.39.1) at 2025-10-15 23:09:29 +0000