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-rw-r--r--src/stm/ao_arch.h28
-rw-r--r--src/stm/ao_beep_stm.c12
-rw-r--r--src/stm/ao_interrupt.c3
-rw-r--r--src/stm/ao_mpu.h29
-rw-r--r--src/stm/ao_mpu_stm.c149
-rw-r--r--src/stm/ao_sample_profile_timer.c115
-rw-r--r--src/stm/ao_sample_profile_timer.h32
-rw-r--r--src/stm/ao_timer.c12
-rw-r--r--src/stm/ao_usb_stm.c38
-rw-r--r--src/stm/registers.ld2
-rw-r--r--src/stm/stm32l.h198
11 files changed, 583 insertions, 35 deletions
diff --git a/src/stm/ao_arch.h b/src/stm/ao_arch.h
index 87eda18b..0c3cfc91 100644
--- a/src/stm/ao_arch.h
+++ b/src/stm/ao_arch.h
@@ -43,7 +43,6 @@
#define __xdata
#define __code const
#define __reentrant
-#define __critical
#define __interrupt(n)
#define __at(n)
@@ -83,8 +82,29 @@ extern const uint32_t ao_radio_cal;
#define ao_arch_task_members\
uint32_t *sp; /* saved stack pointer */
-#define cli() asm("cpsid i")
-#define sei() asm("cpsie i")
+#define ao_arch_block_interrupts() asm("cpsid i")
+#define ao_arch_release_interrupts() asm("cpsie i")
+
+#define cli() ao_arch_block_interrupts()
+#define sei() ao_arch_release_interrupts()
+
+static uint32_t
+ao_arch_irqsave(void) {
+ uint32_t primask;
+ asm("mrs %0,primask" : "=&r" (primask));
+ ao_arch_block_interrupts();
+ return primask;
+}
+
+static void
+ao_arch_irqrestore(uint32_t primask) {
+ asm("msr primask,%0" : : "r" (primask));
+}
+
+static void
+ao_arch_memory_barrier() {
+ asm volatile("" ::: "memory");
+}
#define ao_arch_init_stack(task, start) do { \
uint32_t *sp = (uint32_t *) (task->stack + AO_STACK_SIZE); \
@@ -143,7 +163,7 @@ extern const uint32_t ao_radio_cal;
#define ao_arch_cpu_idle() do { \
- asm("wfi"); \
+ asm(".global ao_idle_loc\n\twfi\nao_idle_loc:"); \
} while (0)
#define ao_arch_restore_stack() do { \
diff --git a/src/stm/ao_beep_stm.c b/src/stm/ao_beep_stm.c
index 37c30e25..4761fbfc 100644
--- a/src/stm/ao_beep_stm.c
+++ b/src/stm/ao_beep_stm.c
@@ -26,15 +26,6 @@ ao_beep(uint8_t beep)
} else {
stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM3EN);
- stm_tim3.cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
- (0 << STM_TIM234_CR1_ARPE) |
- (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) |
- (0 << STM_TIM234_CR1_DIR) |
- (0 << STM_TIM234_CR1_OPM) |
- (0 << STM_TIM234_CR1_URS) |
- (0 << STM_TIM234_CR1_UDIS) |
- (0 << STM_TIM234_CR1_CEN));
-
stm_tim3.cr2 = ((0 << STM_TIM234_CR2_TI1S) |
(STM_TIM234_CR2_MMS_RESET << STM_TIM234_CR2_MMS) |
(0 << STM_TIM234_CR2_CCDS));
@@ -102,6 +93,9 @@ ao_beep(uint8_t beep)
(0 << STM_TIM234_CR1_URS) |
(0 << STM_TIM234_CR1_UDIS) |
(1 << STM_TIM234_CR1_CEN));
+
+ /* Update the values */
+ stm_tim3.egr = (1 << STM_TIM234_EGR_UG);
}
}
diff --git a/src/stm/ao_interrupt.c b/src/stm/ao_interrupt.c
index 6b4a9700..a423d8b1 100644
--- a/src/stm/ao_interrupt.c
+++ b/src/stm/ao_interrupt.c
@@ -15,6 +15,7 @@
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
*/
+#include <ao.h>
#include "stm32l.h"
#include <string.h>
@@ -28,7 +29,7 @@ extern char __bss_start__, __bss_end__;
void stm_halt_isr(void)
{
- for(;;);
+ ao_panic(AO_PANIC_CRASH);
}
void stm_ignore_isr(void)
diff --git a/src/stm/ao_mpu.h b/src/stm/ao_mpu.h
new file mode 100644
index 00000000..cc6132a5
--- /dev/null
+++ b/src/stm/ao_mpu.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright © 2012 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#ifndef _AO_MPU_H_
+#define _AO_MPU_H_
+
+extern uint32_t ao_mpu_dregion;
+
+void
+ao_mpu_stack_guard(void *stack);
+
+void
+ao_mpu_init(void);
+
+#endif /* _AO_MPU_H_ */
diff --git a/src/stm/ao_mpu_stm.c b/src/stm/ao_mpu_stm.c
new file mode 100644
index 00000000..969d7446
--- /dev/null
+++ b/src/stm/ao_mpu_stm.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright © 2012 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#include <ao.h>
+#include <ao_mpu.h>
+
+static uint32_t stm_mpu_dregion;
+
+void
+ao_mpu_init(void)
+{
+ uint32_t region;
+
+ /* Check to see how many regions we have */
+ stm_mpu_dregion = (stm_mpu.typer >> STM_MPU_TYPER_DREGION) & STM_MPU_TYPER_DREGION_MASK;
+
+ /* No MPU at all */
+ if (stm_mpu_dregion == 0)
+ return;
+
+ /* Disable MPU */
+ stm_mpu.cr = ((0 << STM_MPU_CR_PRIVDEFENA) |
+ (0 << STM_MPU_CR_HFNMIENA) |
+ (0 << STM_MPU_CR_ENABLE));
+
+ /* Disable all regions */
+ for (region = 0; region < stm_mpu_dregion; region++) {
+ /* Set the base address and RNR value */
+ stm_mpu.rbar = ((0 & (STM_MPU_RBAR_ADDR_MASK << STM_MPU_RBAR_ADDR)) |
+ (1 << STM_MPU_RBAR_VALID) |
+ (region << STM_MPU_RBAR_REGION));
+
+ /* Disable this region */
+ stm_mpu.rasr = 0;
+ }
+
+ region = 0;
+
+ /* Flash */
+ /* 0x00000000 - 0x1fffffff */
+ stm_mpu.rbar = (0x0000000 |
+ (1 << STM_MPU_RBAR_VALID) |
+ (region << STM_MPU_RBAR_REGION));
+
+ stm_mpu.rasr = ((0 << STM_MPU_RASR_XN) |
+ (STM_MPU_RASR_AP_RO_RO << STM_MPU_RASR_AP) |
+ (5 << STM_MPU_RASR_TEX) |
+ (0 << STM_MPU_RASR_C) |
+ (1 << STM_MPU_RASR_B) |
+ (0 << STM_MPU_RASR_S) |
+ (0 << STM_MPU_RASR_SRD) |
+ (28 << STM_MPU_RASR_SIZE) |
+ (1 << STM_MPU_RASR_ENABLE));
+ region++;
+
+ /* Ram */
+ /* 0x20000000 - 0x3fffffff */
+ stm_mpu.rbar = (0x20000000 |
+ (1 << STM_MPU_RBAR_VALID) |
+ (region << STM_MPU_RBAR_REGION));
+
+ stm_mpu.rasr = ((0 << STM_MPU_RASR_XN) |
+ (STM_MPU_RASR_AP_RW_RW << STM_MPU_RASR_AP) |
+ (5 << STM_MPU_RASR_TEX) |
+ (0 << STM_MPU_RASR_C) |
+ (1 << STM_MPU_RASR_B) |
+ (0 << STM_MPU_RASR_S) |
+ (0 << STM_MPU_RASR_SRD) |
+ (28 << STM_MPU_RASR_SIZE) |
+ (1 << STM_MPU_RASR_ENABLE));
+ region++;
+
+ /* Peripherals */
+
+ /* 0x4000000 - 0x7ffffff */
+ stm_mpu.rbar = (0x40000000 |
+ (1 << STM_MPU_RBAR_VALID) |
+ (region << STM_MPU_RBAR_REGION));
+
+ stm_mpu.rasr = ((1 << STM_MPU_RASR_XN) |
+ (STM_MPU_RASR_AP_RW_RW << STM_MPU_RASR_AP) |
+ (2 << STM_MPU_RASR_TEX) |
+ (0 << STM_MPU_RASR_C) |
+ (0 << STM_MPU_RASR_B) |
+ (0 << STM_MPU_RASR_S) |
+ (0 << STM_MPU_RASR_SRD) |
+ (29 << STM_MPU_RASR_SIZE) |
+ (1 << STM_MPU_RASR_ENABLE));
+ region++;
+
+ /* 0x8000000 - 0xffffffff */
+ stm_mpu.rbar = (0x80000000 |
+ (1 << STM_MPU_RBAR_VALID) |
+ (region << STM_MPU_RBAR_REGION));
+
+ stm_mpu.rasr = ((1 << STM_MPU_RASR_XN) |
+ (STM_MPU_RASR_AP_RW_RW << STM_MPU_RASR_AP) |
+ (2 << STM_MPU_RASR_TEX) |
+ (0 << STM_MPU_RASR_C) |
+ (0 << STM_MPU_RASR_B) |
+ (0 << STM_MPU_RASR_S) |
+ (0 << STM_MPU_RASR_SRD) |
+ (30 << STM_MPU_RASR_SIZE) |
+ (1 << STM_MPU_RASR_ENABLE));
+ region++;
+
+ /* Enable MPU */
+ stm_mpu.cr = ((0 << STM_MPU_CR_PRIVDEFENA) |
+ (0 << STM_MPU_CR_HFNMIENA) |
+ (1 << STM_MPU_CR_ENABLE));
+}
+
+/*
+ * Protect the base of the stack from CPU access
+ */
+
+void
+ao_mpu_stack_guard(void *base)
+{
+ uintptr_t addr = (uintptr_t) base;
+
+ /* Round up to cover the lowest possible 32-byte region */
+ addr = (addr + ~(STM_MPU_RBAR_ADDR_MASK << STM_MPU_RBAR_ADDR)) & (STM_MPU_RBAR_ADDR_MASK << STM_MPU_RBAR_ADDR);
+
+ stm_mpu.rbar = addr | (1 << STM_MPU_RBAR_VALID) | (7 << STM_MPU_RBAR_REGION);
+ stm_mpu.rasr = ((1 << STM_MPU_RASR_XN) |
+ (STM_MPU_RASR_AP_NONE_NONE << STM_MPU_RASR_AP) |
+ (5 << STM_MPU_RASR_TEX) |
+ (0 << STM_MPU_RASR_C) |
+ (1 << STM_MPU_RASR_B) |
+ (0 << STM_MPU_RASR_S) |
+ (0 << STM_MPU_RASR_SRD) |
+ (4 << STM_MPU_RASR_SIZE) |
+ (1 << STM_MPU_RASR_ENABLE));
+}
diff --git a/src/stm/ao_sample_profile_timer.c b/src/stm/ao_sample_profile_timer.c
new file mode 100644
index 00000000..d5af3a57
--- /dev/null
+++ b/src/stm/ao_sample_profile_timer.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright © 2012 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#include <ao.h>
+#include <ao_sample_profile.h>
+
+struct stm_exception {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r12;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t psr;
+};
+
+void
+stm_tim10_isr(void)
+{
+ struct stm_exception *ex;
+
+ asm("mov %0,sp" : "=&r" (ex));
+
+ stm_tim10.sr = 0;
+ ao_sample_profile_point(ex->pc, stm_tim11.cnt, (ex->psr & 0xff) != 0);
+}
+
+uint16_t
+ao_sample_profile_timer_start(void)
+{
+ /* Reset counts */
+ stm_tim11.cnt = 0;
+ stm_tim10.cnt = 0;
+
+ /* Turn on timer 11 */
+ stm_tim11.cr1 = ((0 << STM_TIM1011_CR1_CKD) |
+ (0 << STM_TIM1011_CR1_ARPE) |
+ (1 << STM_TIM1011_CR1_URS) |
+ (0 << STM_TIM1011_CR1_UDIS) |
+ (1 << STM_TIM1011_CR1_CEN));
+
+ /* Turn on timer 10 */
+ stm_tim10.cr1 = ((0 << STM_TIM1011_CR1_CKD) |
+ (0 << STM_TIM1011_CR1_ARPE) |
+ (1 << STM_TIM1011_CR1_URS) |
+ (0 << STM_TIM1011_CR1_UDIS) |
+ (1 << STM_TIM1011_CR1_CEN));
+ return stm_tim11.cnt;
+}
+
+void
+ao_sample_profile_timer_stop(void)
+{
+ stm_tim10.cr1 = 0;
+ stm_tim11.cr1 = 0;
+}
+
+#if AO_APB2_PRESCALER > 1
+#define TIMER_91011_SCALER 2
+#else
+#define TIMER_91011_SCALER 1
+#endif
+
+#define TIMER_10kHz ((AO_PCLK2 * TIMER_91011_SCALER) / 10000)
+#define TIMER_1kHz ((AO_PCLK2 * TIMER_91011_SCALER) / 1000)
+
+void
+ao_sample_profile_timer_init(void)
+{
+ /* Turn on power for timer 10 and 11 */
+ stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_TIM10EN) | (1 << STM_RCC_APB2ENR_TIM11EN);
+
+ /* Timer 10 is the 1kHz interrupt */
+ stm_tim10.cr1 = 0;
+ stm_tim10.psc = TIMER_10kHz;
+ stm_tim10.arr = 9;
+ stm_tim10.cnt = 0;
+
+ /* Enable timer 10 update interrupt */
+ stm_tim10.dier = (1 << STM_TIM1011_DIER_UIE);
+
+ /* Poke timer to reload values */
+ stm_tim10.egr |= (1 << STM_TIM1011_EGR_UG);
+
+ /* Timer 11 is the 1kHz counter */
+ stm_tim11.cr1 = 0;
+ stm_tim11.psc = TIMER_1kHz;
+ stm_tim11.arr = 0xffff;
+ stm_tim11.cnt = 0;
+
+ /* Disable interrupts for timer 11 */
+ stm_tim11.dier = 0;
+
+ /* Poke timer to reload values */
+ stm_tim11.egr |= (1 << STM_TIM1011_EGR_UG);
+
+ stm_tim10.sr = 0;
+ stm_nvic_set_enable(STM_ISR_TIM10_POS);
+ stm_nvic_set_priority(STM_ISR_TIM10_POS, AO_STM_NVIC_HIGH_PRIORITY);
+}
diff --git a/src/stm/ao_sample_profile_timer.h b/src/stm/ao_sample_profile_timer.h
new file mode 100644
index 00000000..1da1bfb4
--- /dev/null
+++ b/src/stm/ao_sample_profile_timer.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright © 2012 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#ifndef _AO_SAMPLE_PROFILE_TIMER_H_
+#define _AO_SAMPLE_PROFILE_TIMER_H_
+
+uint16_t
+ao_sample_profile_timer_start(void);
+
+void
+ao_sample_profile_timer_stop(void);
+
+void
+ao_sample_profile_timer_init(void);
+
+#define ao_sample_profile_timer_value() ((uint16_t) stm_tim11.cnt)
+
+#endif /* _AO_SAMPLE_PROFILE_TIMER_H_ */
diff --git a/src/stm/ao_timer.c b/src/stm/ao_timer.c
index f3011d3f..d69035f8 100644
--- a/src/stm/ao_timer.c
+++ b/src/stm/ao_timer.c
@@ -16,6 +16,7 @@
*/
#include "ao.h"
+#include <ao_task.h>
volatile __data AO_TICK_TYPE ao_tick_count;
@@ -42,6 +43,9 @@ void stm_tim6_isr(void)
if (stm_tim6.sr & (1 << STM_TIM67_SR_UIF)) {
stm_tim6.sr = 0;
++ao_tick_count;
+#if HAS_TASK_QUEUE
+ ao_task_check_alarm((uint16_t) ao_tick_count);
+#endif
#if AO_DATA_ALL
if (++ao_data_count == ao_data_interval) {
ao_data_count = 0;
@@ -56,10 +60,12 @@ void stm_tim6_isr(void)
#if HAS_ADC
void
-ao_timer_set_adc_interval(uint8_t interval) __critical
+ao_timer_set_adc_interval(uint8_t interval)
{
- ao_data_interval = interval;
- ao_data_count = 0;
+ ao_arch_critical(
+ ao_data_interval = interval;
+ ao_data_count = 0;
+ );
}
#endif
diff --git a/src/stm/ao_usb_stm.c b/src/stm/ao_usb_stm.c
index 4f37a7d9..8e7dacc5 100644
--- a/src/stm/ao_usb_stm.c
+++ b/src/stm/ao_usb_stm.c
@@ -799,25 +799,23 @@ ao_usb_in_send(void)
ao_usb_tx_count = 0;
}
-/* Wait for a free IN buffer */
+/* Wait for a free IN buffer. Interrupts are blocked */
static void
-ao_usb_in_wait(void)
+_ao_usb_in_wait(void)
{
for (;;) {
/* Check if the current buffer is writable */
if (ao_usb_tx_count < AO_USB_IN_SIZE)
break;
- cli();
/* Wait for an IN buffer to be ready */
while (ao_usb_in_pending)
ao_sleep(&ao_usb_in_pending);
- sei();
}
}
void
-ao_usb_flush(void) __critical
+ao_usb_flush(void)
{
if (!ao_usb_running)
return;
@@ -829,24 +827,25 @@ ao_usb_flush(void) __critical
* packet was full, in which case we now
* want to send an empty packet
*/
+ ao_arch_block_interrupts();
if (!ao_usb_in_flushed) {
ao_usb_in_flushed = 1;
- cli();
/* Wait for an IN buffer to be ready */
while (ao_usb_in_pending)
ao_sleep(&ao_usb_in_pending);
- sei();
ao_usb_in_send();
}
+ ao_arch_release_interrupts();
}
void
-ao_usb_putchar(char c) __critical __reentrant
+ao_usb_putchar(char c)
{
if (!ao_usb_running)
return;
- ao_usb_in_wait();
+ ao_arch_block_interrupts();
+ _ao_usb_in_wait();
ao_usb_in_flushed = 0;
ao_usb_tx_buffer[ao_usb_tx_count++] = (uint8_t) c;
@@ -854,10 +853,11 @@ ao_usb_putchar(char c) __critical __reentrant
/* Send the packet when full */
if (ao_usb_tx_count == AO_USB_IN_SIZE)
ao_usb_in_send();
+ ao_arch_release_interrupts();
}
static void
-ao_usb_out_recv(void)
+_ao_usb_out_recv(void)
{
ao_usb_out_avail = 0;
@@ -888,7 +888,7 @@ _ao_usb_pollchar(void)
/* Check to see if a packet has arrived */
if (!ao_usb_out_avail)
return AO_READ_AGAIN;
- ao_usb_out_recv();
+ _ao_usb_out_recv();
}
/* Pull a character out of the fifo */
@@ -900,27 +900,28 @@ char
ao_usb_pollchar(void)
{
char c;
- cli();
+ ao_arch_block_interrupts();
c = _ao_usb_pollchar();
- sei();
+ ao_arch_release_interrupts();
return c;
}
char
-ao_usb_getchar(void) __critical
+ao_usb_getchar(void)
{
char c;
- cli();
+ ao_arch_block_interrupts();
while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
ao_sleep(&ao_stdin_ready);
- sei();
+ ao_arch_release_interrupts();
return c;
}
void
ao_usb_disable(void)
{
+ ao_arch_block_interrupts();
stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
stm_usb.istr = 0;
@@ -932,6 +933,7 @@ ao_usb_disable(void)
/* Disable the interface */
stm_rcc.apb1enr &+ ~(1 << STM_RCC_APB1ENR_USBEN);
+ ao_arch_release_interrupts();
}
void
@@ -954,6 +956,8 @@ ao_usb_enable(void)
* pulled low and doesn't work at all
*/
+ ao_arch_block_interrupts();
+
/* Route interrupts */
stm_nvic_set_priority(STM_ISR_USB_LP_POS, 3);
stm_nvic_set_enable(STM_ISR_USB_LP_POS);
@@ -985,6 +989,8 @@ ao_usb_enable(void)
(0 << STM_USB_CNTR_PDWN) |
(0 << STM_USB_CNTR_FRES));
+ ao_arch_release_interrupts();
+
for (t = 0; t < 1000; t++)
ao_arch_nop();
/* Enable USB pull-up */
diff --git a/src/stm/registers.ld b/src/stm/registers.ld
index fd61e486..f8b224a2 100644
--- a/src/stm/registers.ld
+++ b/src/stm/registers.ld
@@ -46,5 +46,7 @@ stm_tim2 = 0x40000000;
stm_nvic = 0xe000e100;
+stm_mpu = 0xe000ed90;
+
/* calibration data in system memory */
stm_temp_cal = 0x1ff80078;
diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h
index 25f5af07..d953aee4 100644
--- a/src/stm/stm32l.h
+++ b/src/stm/stm32l.h
@@ -254,8 +254,138 @@ struct stm_tim {
};
extern struct stm_tim stm_tim9;
-extern struct stm_tim stm_tim10;
-extern struct stm_tim stm_tim11;
+
+struct stm_tim1011 {
+ vuint32_t cr1;
+ uint32_t unused_4;
+ vuint32_t smcr;
+ vuint32_t dier;
+ vuint32_t sr;
+ vuint32_t egr;
+ vuint32_t ccmr1;
+ uint32_t unused_1c;
+ vuint32_t ccer;
+ vuint32_t cnt;
+ vuint32_t psc;
+ vuint32_t arr;
+ uint32_t unused_30;
+ vuint32_t ccr1;
+ uint32_t unused_38;
+ uint32_t unused_3c;
+ uint32_t unused_40;
+ uint32_t unused_44;
+ uint32_t unused_48;
+ uint32_t unused_4c;
+ vuint32_t or;
+};
+
+extern struct stm_tim1011 stm_tim10;
+extern struct stm_tim1011 stm_tim11;
+
+#define STM_TIM1011_CR1_CKD 8
+#define STM_TIM1011_CR1_CKD_1 0
+#define STM_TIM1011_CR1_CKD_2 1
+#define STM_TIM1011_CR1_CKD_4 2
+#define STM_TIM1011_CR1_CKD_MASK 3
+#define STM_TIM1011_CR1_ARPE 7
+#define STM_TIM1011_CR1_URS 2
+#define STM_TIM1011_CR1_UDIS 1
+#define STM_TIM1011_CR1_CEN 0
+
+#define STM_TIM1011_SMCR_ETP 15
+#define STM_TIM1011_SMCR_ECE 14
+#define STM_TIM1011_SMCR_ETPS 12
+#define STM_TIM1011_SMCR_ETPS_OFF 0
+#define STM_TIM1011_SMCR_ETPS_2 1
+#define STM_TIM1011_SMCR_ETPS_4 2
+#define STM_TIM1011_SMCR_ETPS_8 3
+#define STM_TIM1011_SMCR_ETPS_MASK 3
+#define STM_TIM1011_SMCR_ETF 8
+#define STM_TIM1011_SMCR_ETF_NONE 0
+#define STM_TIM1011_SMCR_ETF_CK_INT_2 1
+#define STM_TIM1011_SMCR_ETF_CK_INT_4 2
+#define STM_TIM1011_SMCR_ETF_CK_INT_8 3
+#define STM_TIM1011_SMCR_ETF_DTS_2_6 4
+#define STM_TIM1011_SMCR_ETF_DTS_2_8 5
+#define STM_TIM1011_SMCR_ETF_DTS_4_6 6
+#define STM_TIM1011_SMCR_ETF_DTS_4_8 7
+#define STM_TIM1011_SMCR_ETF_DTS_8_6 8
+#define STM_TIM1011_SMCR_ETF_DTS_8_8 9
+#define STM_TIM1011_SMCR_ETF_DTS_16_5 10
+#define STM_TIM1011_SMCR_ETF_DTS_16_6 11
+#define STM_TIM1011_SMCR_ETF_DTS_16_8 12
+#define STM_TIM1011_SMCR_ETF_DTS_32_5 13
+#define STM_TIM1011_SMCR_ETF_DTS_32_6 14
+#define STM_TIM1011_SMCR_ETF_DTS_32_8 15
+#define STM_TIM1011_SMCR_ETF_MASK 15
+
+#define STM_TIM1011_DIER_CC1E 1
+#define STM_TIM1011_DIER_UIE 0
+
+#define STM_TIM1011_SR_CC1OF 9
+#define STM_TIM1011_SR_CC1IF 1
+#define STM_TIM1011_SR_UIF 0
+
+#define STM_TIM1011_EGR_CC1G 1
+#define STM_TIM1011_EGR_UG 0
+
+#define STM_TIM1011_CCMR1_OC1CE 7
+#define STM_TIM1011_CCMR1_OC1M 4
+#define STM_TIM1011_CCMR1_OC1M_FROZEN 0
+#define STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH 1
+#define STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
+#define STM_TIM1011_CCMR1_OC1M_TOGGLE 3
+#define STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE 4
+#define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
+#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
+#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
+#define STM_TIM1011_CCMR1_OC1M_MASK 7
+#define STM_TIM1011_CCMR1_OC1PE 3
+#define STM_TIM1011_CCMR1_OC1FE 2
+#define STM_TIM1011_CCMR1_CC1S 0
+#define STM_TIM1011_CCMR1_CC1S_OUTPUT 0
+#define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
+#define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
+#define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
+#define STM_TIM1011_CCMR1_CC1S_MASK 3
+
+#define STM_TIM1011_CCMR1_IC1F_NONE 0
+#define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
+#define STM_TIM1011_CCMR1_IC1F_CK_INT_4 2
+#define STM_TIM1011_CCMR1_IC1F_CK_INT_8 3
+#define STM_TIM1011_CCMR1_IC1F_DTS_2_6 4
+#define STM_TIM1011_CCMR1_IC1F_DTS_2_8 5
+#define STM_TIM1011_CCMR1_IC1F_DTS_4_6 6
+#define STM_TIM1011_CCMR1_IC1F_DTS_4_8 7
+#define STM_TIM1011_CCMR1_IC1F_DTS_8_6 8
+#define STM_TIM1011_CCMR1_IC1F_DTS_8_8 9
+#define STM_TIM1011_CCMR1_IC1F_DTS_16_5 10
+#define STM_TIM1011_CCMR1_IC1F_DTS_16_6 11
+#define STM_TIM1011_CCMR1_IC1F_DTS_16_8 12
+#define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
+#define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
+#define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
+#define STM_TIM1011_CCMR1_IC1F_MASK 15
+#define STM_TIM1011_CCMR1_IC1PSC 2
+#define STM_TIM1011_CCMR1_IC1PSC_1 0
+#define STM_TIM1011_CCMR1_IC1PSC_2 1
+#define STM_TIM1011_CCMR1_IC1PSC_4 2
+#define STM_TIM1011_CCMR1_IC1PSC_8 3
+#define STM_TIM1011_CCMR1_IC1PSC_MASK 3
+#define STM_TIM1011_CCMR1_CC1S 0
+
+#define STM_TIM1011_CCER_CC1NP 3
+#define STM_TIM1011_CCER_CC1P 1
+#define STM_TIM1011_CCER_CC1E 0
+
+#define STM_TIM1011_OR_TI1_RMP_RI 3
+#define STM_TIM1011_ETR_RMP 2
+#define STM_TIM1011_TI1_RMP 0
+#define STM_TIM1011_TI1_RMP_GPIO 0
+#define STM_TIM1011_TI1_RMP_LSI 1
+#define STM_TIM1011_TI1_RMP_LSE 2
+#define STM_TIM1011_TI1_RMP_RTC 3
+#define STM_TIM1011_TI1_RMP_MASK 3
/* Flash interface */
@@ -771,6 +901,63 @@ stm_nvic_get_priority(int irq) {
return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
}
+struct stm_mpu {
+ vuint32_t typer;
+ vuint32_t cr;
+ vuint32_t rnr;
+ vuint32_t rbar;
+
+ vuint32_t rasr;
+ vuint32_t rbar_a1;
+ vuint32_t rasr_a1;
+ vuint32_t rbar_a2;
+ vuint32_t rasr_a2;
+ vuint32_t rbar_a3;
+ vuint32_t rasr_a3;
+};
+
+extern struct stm_mpu stm_mpu;
+
+#define STM_MPU_TYPER_IREGION 16
+#define STM_MPU_TYPER_IREGION_MASK 0xff
+#define STM_MPU_TYPER_DREGION 8
+#define STM_MPU_TYPER_DREGION_MASK 0xff
+#define STM_MPU_TYPER_SEPARATE 0
+
+#define STM_MPU_CR_PRIVDEFENA 2
+#define STM_MPU_CR_HFNMIENA 1
+#define STM_MPU_CR_ENABLE 0
+
+#define STM_MPU_RNR_REGION 0
+#define STM_MPU_RNR_REGION_MASK 0xff
+
+#define STM_MPU_RBAR_ADDR 5
+#define STM_MPU_RBAR_ADDR_MASK 0x7ffffff
+
+#define STM_MPU_RBAR_VALID 4
+#define STM_MPU_RBAR_REGION 0
+#define STM_MPU_RBAR_REGION_MASK 0xf
+
+#define STM_MPU_RASR_XN 28
+#define STM_MPU_RASR_AP 24
+#define STM_MPU_RASR_AP_NONE_NONE 0
+#define STM_MPU_RASR_AP_RW_NONE 1
+#define STM_MPU_RASR_AP_RW_RO 2
+#define STM_MPU_RASR_AP_RW_RW 3
+#define STM_MPU_RASR_AP_RO_NONE 5
+#define STM_MPU_RASR_AP_RO_RO 6
+#define STM_MPU_RASR_AP_MASK 7
+#define STM_MPU_RASR_TEX 19
+#define STM_MPU_RASR_TEX_MASK 7
+#define STM_MPU_RASR_S 18
+#define STM_MPU_RASR_C 17
+#define STM_MPU_RASR_B 16
+#define STM_MPU_RASR_SRD 8
+#define STM_MPU_RASR_SRD_MASK 0xff
+#define STM_MPU_RASR_SIZE 1
+#define STM_MPU_RASR_SIZE_MASK 0x1f
+#define STM_MPU_RASR_ENABLE 0
+
#define isr(name) void stm_ ## name ## _isr(void);
isr(nmi)
@@ -1438,6 +1625,13 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
#define STM_TIM234_SR_CC1IF 1
#define STM_TIM234_SR_UIF 0
+#define STM_TIM234_EGR_TG 6
+#define STM_TIM234_EGR_CC4G 4
+#define STM_TIM234_EGR_CC3G 3
+#define STM_TIM234_EGR_CC2G 2
+#define STM_TIM234_EGR_CC1G 1
+#define STM_TIM234_EGR_UG 0
+
#define STM_TIM234_CCMR1_OC2CE 15
#define STM_TIM234_CCMR1_OC2M 12
#define STM_TIM234_CCMR1_OC2M_FROZEN 0
generated by cgit v1.2.3 (git 2.39.1) at 2025-11-02 21:15:33 +0000