diff options
| -rw-r--r-- | src/ao.h | 16 | ||||
| -rw-r--r-- | src/ao_adc.c | 2 | ||||
| -rw-r--r-- | src/ao_cmd.c | 3 | ||||
| -rw-r--r-- | src/ao_dma.c | 2 | ||||
| -rw-r--r-- | src/ao_radio.c | 2 | ||||
| -rw-r--r-- | src/ao_serial.c | 4 | ||||
| -rw-r--r-- | src/ao_timer.c | 2 | ||||
| -rw-r--r-- | src/ao_usb.c | 2 | ||||
| -rw-r--r-- | src/cc1111.h | 108 |
9 files changed, 70 insertions, 71 deletions
@@ -79,7 +79,7 @@ ao_alarm(uint16_t delay); /* Yield the processor to another task */ void -ao_yield(void) _naked; +ao_yield(void) __naked; /* Add a task to the run queue */ void @@ -139,7 +139,7 @@ ao_timer_set_adc_interval(uint8_t interval) __critical; /* Timer interrupt */ void -ao_timer_isr(void) interrupt 9; +ao_timer_isr(void) __interrupt 9; /* Initialize the timer */ void @@ -198,7 +198,7 @@ ao_adc_get(__xdata struct ao_adc *packet); /* The A/D interrupt handler */ void -ao_adc_isr(void) interrupt 1; +ao_adc_isr(void) __interrupt 1; /* Initialize the A/D converter */ void @@ -325,7 +325,7 @@ ao_usb_flush(void); /* USB interrupt handler */ void -ao_usb_isr(void) interrupt 6; +ao_usb_isr(void) __interrupt 6; /* Enable the USB controller */ void @@ -425,7 +425,7 @@ ao_dma_abort(uint8_t id); /* DMA interrupt routine */ void -ao_dma_isr(void) interrupt 8; +ao_dma_isr(void) __interrupt 8; /* * ao_mutex.c @@ -722,10 +722,10 @@ ao_dbg_init(void); #if HAS_SERIAL_1 void -ao_serial_rx1_isr(void) interrupt 3; +ao_serial_rx1_isr(void) __interrupt 3; void -ao_serial_tx1_isr(void) interrupt 14; +ao_serial_tx1_isr(void) __interrupt 14; char ao_serial_getchar(void) __critical; @@ -861,7 +861,7 @@ extern __xdata uint8_t ao_radio_done; extern __xdata uint8_t ao_radio_mutex; void -ao_radio_general_isr(void) interrupt 16; +ao_radio_general_isr(void) __interrupt 16; void ao_radio_get(void); diff --git a/src/ao_adc.c b/src/ao_adc.c index 50f96848..49d2519e 100644 --- a/src/ao_adc.c +++ b/src/ao_adc.c @@ -41,7 +41,7 @@ ao_adc_get(__xdata struct ao_adc *packet) } void -ao_adc_isr(void) interrupt 1 +ao_adc_isr(void) __interrupt 1 { uint8_t sequence; uint8_t __xdata *a; diff --git a/src/ao_cmd.c b/src/ao_cmd.c index 4a68fba4..a54a2316 100644 --- a/src/ao_cmd.c +++ b/src/ao_cmd.c @@ -263,13 +263,12 @@ ao_cmd_register(__code struct ao_cmds *cmds) } void -ao_cmd(void *parameters) +ao_cmd(void) { __xdata char c; __xdata uint8_t cmd, cmds; __code struct ao_cmds * __xdata cs; void (*__xdata func)(void); - (void) parameters; lex_echo = 1; for (;;) { diff --git a/src/ao_dma.c b/src/ao_dma.c index 110138b5..946666ab 100644 --- a/src/ao_dma.c +++ b/src/ao_dma.c @@ -112,7 +112,7 @@ ao_dma_abort(uint8_t id) } void -ao_dma_isr(void) interrupt 8 +ao_dma_isr(void) __interrupt 8 { uint8_t id, mask; diff --git a/src/ao_radio.c b/src/ao_radio.c index 0849349e..f4a9d3b2 100644 --- a/src/ao_radio.c +++ b/src/ao_radio.c @@ -275,7 +275,7 @@ __xdata uint8_t ao_radio_done; __xdata uint8_t ao_radio_mutex; void -ao_radio_general_isr(void) interrupt 16 +ao_radio_general_isr(void) __interrupt 16 { S1CON &= ~0x03; if (RFIF & RFIF_IM_TIMEOUT) { diff --git a/src/ao_serial.c b/src/ao_serial.c index 3f103766..a48734c2 100644 --- a/src/ao_serial.c +++ b/src/ao_serial.c @@ -21,7 +21,7 @@ volatile __xdata struct ao_fifo ao_usart1_rx_fifo; volatile __xdata struct ao_fifo ao_usart1_tx_fifo; void -ao_serial_rx1_isr(void) interrupt 3 +ao_serial_rx1_isr(void) __interrupt 3 { if (!ao_fifo_full(ao_usart1_rx_fifo)) ao_fifo_insert(ao_usart1_rx_fifo, U1DBUF); @@ -42,7 +42,7 @@ ao_serial_tx1_start(void) } void -ao_serial_tx1_isr(void) interrupt 14 +ao_serial_tx1_isr(void) __interrupt 14 { UTX1IF = 0; ao_serial_tx1_started = 0; diff --git a/src/ao_timer.c b/src/ao_timer.c index d1731475..c977fbc8 100644 --- a/src/ao_timer.c +++ b/src/ao_timer.c @@ -41,7 +41,7 @@ volatile __data uint8_t ao_adc_interval = 1; volatile __data uint8_t ao_adc_count; #endif -void ao_timer_isr(void) interrupt 9 +void ao_timer_isr(void) __interrupt 9 { ++ao_tick_count; #if HAS_ADC diff --git a/src/ao_usb.c b/src/ao_usb.c index f6e0fcf9..b55130f2 100644 --- a/src/ao_usb.c +++ b/src/ao_usb.c @@ -43,7 +43,7 @@ ao_usb_set_interrupts(void) * so when we hook that up, fix this */ void -ao_usb_isr(void) interrupt 6 +ao_usb_isr(void) __interrupt 6 { USBIF = 0; ao_usb_iif |= USBIIF; diff --git a/src/cc1111.h b/src/cc1111.h index e8302df2..20ed052a 100644 --- a/src/cc1111.h +++ b/src/cc1111.h @@ -40,16 +40,16 @@ #include <cc1110.h> #include <stdint.h> -sfr at 0xA8 IEN0; /* Interrupt Enable 0 Register */ +sfr __at 0xA8 IEN0; /* Interrupt Enable 0 Register */ -sbit at 0xA8 RFTXRXIE; /* RF TX/RX done interrupt enable */ -sbit at 0xA9 ADCIE; /* ADC interrupt enable */ -sbit at 0xAA URX0IE; /* USART0 RX interrupt enable */ -sbit at 0xAB URX1IE; /* USART1 RX interrupt enable (shared with I2S RX) */ -sbit at 0xAB I2SRXIE; /* I2S RX interrupt enable (shared with USART1 RX) */ -sbit at 0xAC ENCIE; /* AES encryption/decryption interrupt enable */ -sbit at 0xAD STIE; /* Sleep Timer interrupt enable */ -sbit at 0xAF EA; /* Enable All */ +sbit __at 0xA8 RFTXRXIE; /* RF TX/RX done interrupt enable */ +sbit __at 0xA9 ADCIE; /* ADC interrupt enable */ +sbit __at 0xAA URX0IE; /* USART0 RX interrupt enable */ +sbit __at 0xAB URX1IE; /* USART1 RX interrupt enable (shared with I2S RX) */ +sbit __at 0xAB I2SRXIE; /* I2S RX interrupt enable (shared with USART1 RX) */ +sbit __at 0xAC ENCIE; /* AES encryption/decryption interrupt enable */ +sbit __at 0xAD STIE; /* Sleep Timer interrupt enable */ +sbit __at 0xAF EA; /* Enable All */ #define IEN0_EA (1 << 7) #define IEN0_STIE (1 << 5) @@ -60,7 +60,7 @@ sbit at 0xAF EA; /* Enable All */ #define IEN0_ADCIE (1 << 1) #define IEN0_RFTXRXIE (1 << 0) -sfr at 0xB8 IEN1; /* Interrupt Enable 1 Register */ +sfr __at 0xB8 IEN1; /* Interrupt Enable 1 Register */ #define IEN1_P0IE (1 << 5) /* Port 0 interrupt enable */ #define IEN1_T4IE (1 << 4) /* Timer 4 interrupt enable */ @@ -70,7 +70,7 @@ sfr at 0xB8 IEN1; /* Interrupt Enable 1 Register */ #define IEN1_DMAIE (1 << 0) /* DMA transfer interrupt enable */ /* IEN2 */ -sfr at 0x9A IEN2; /* Interrupt Enable 2 Register */ +sfr __at 0x9A IEN2; /* Interrupt Enable 2 Register */ #define IEN2_WDTIE (1 << 5) /* Watchdog timer interrupt enable */ #define IEN2_P1IE (1 << 4) /* Port 1 interrupt enable */ @@ -82,7 +82,7 @@ sfr at 0x9A IEN2; /* Interrupt Enable 2 Register */ #define IEN2_RFIE (1 << 0) /* RF general interrupt enable */ /* CLKCON 0xC6 */ -sfr at 0xC6 CLKCON; /* Clock Control */ +sfr __at 0xC6 CLKCON; /* Clock Control */ #define CLKCON_OSC32K_RC (1 << 7) #define CLKCON_OSC32K_XTAL (0 << 7) @@ -126,20 +126,20 @@ sfr at 0xC6 CLKCON; /* Clock Control */ #define SLEEP_MODE_MASK (3 << 0) /* PCON 0x87 */ -sfr at 0x87 PCON; /* Power Mode Control Register */ +sfr __at 0x87 PCON; /* Power Mode Control Register */ #define PCON_IDLE (1 << 0) /* * TCON */ -sfr at 0x88 TCON; /* CPU Interrupt Flag 1 */ +sfr __at 0x88 TCON; /* CPU Interrupt Flag 1 */ -sbit at 0x8F URX1IF; /* USART1 RX interrupt flag. Automatically cleared */ -sbit at 0x8F I2SRXIF; /* I2S RX interrupt flag. Automatically cleared */ -sbit at 0x8D ADCIF; /* ADC interrupt flag. Automatically cleared */ -sbit at 0x8B URX0IF; /* USART0 RX interrupt flag. Automatically cleared */ -sbit at 0x89 RFTXRXIF; /* RF TX/RX complete interrupt flag. Automatically cleared */ +sbit __at 0x8F URX1IF; /* USART1 RX interrupt flag. Automatically cleared */ +sbit __at 0x8F I2SRXIF; /* I2S RX interrupt flag. Automatically cleared */ +sbit __at 0x8D ADCIF; /* ADC interrupt flag. Automatically cleared */ +sbit __at 0x8B URX0IF; /* USART0 RX interrupt flag. Automatically cleared */ +sbit __at 0x89 RFTXRXIF; /* RF TX/RX complete interrupt flag. Automatically cleared */ #define TCON_URX1IF (1 << 7) #define TCON_I2SRXIF (1 << 7) @@ -150,10 +150,10 @@ sbit at 0x89 RFTXRXIF; /* RF TX/RX complete interrupt flag. Automatically cleare /* * S0CON */ -sfr at 0x98 S0CON; /* CPU Interrupt Flag 2 */ +sfr __at 0x98 S0CON; /* CPU Interrupt Flag 2 */ -sbit at 0x98 ENCIF_0; /* AES interrupt 0. */ -sbit at 0x99 ENCIF_1; /* AES interrupt 1. */ +sbit __at 0x98 ENCIF_0; /* AES interrupt 0. */ +sbit __at 0x99 ENCIF_1; /* AES interrupt 1. */ #define S0CON_ENCIF_1 (1 << 1) #define S0CON_ENCIF_0 (1 << 0) @@ -161,7 +161,7 @@ sbit at 0x99 ENCIF_1; /* AES interrupt 1. */ /* * S1CON */ -sfr at 0x9B S1CON; /* CPU Interrupt Flag 3 */ +sfr __at 0x9B S1CON; /* CPU Interrupt Flag 3 */ #define S1CON_RFIF_1 (1 << 1) #define S1CON_RFIF_0 (1 << 0) @@ -169,15 +169,15 @@ sfr at 0x9B S1CON; /* CPU Interrupt Flag 3 */ /* * IRCON */ -sfr at 0xC0 IRCON; /* CPU Interrupt Flag 4 */ +sfr __at 0xC0 IRCON; /* CPU Interrupt Flag 4 */ -sbit at 0xC0 DMAIF; /* DMA complete interrupt flag */ -sbit at 0xC1 T1IF; /* Timer 1 interrupt flag. Automatically cleared */ -sbit at 0xC2 T2IF; /* Timer 2 interrupt flag. Automatically cleared */ -sbit at 0xC3 T3IF; /* Timer 3 interrupt flag. Automatically cleared */ -sbit at 0xC4 T4IF; /* Timer 4 interrupt flag. Automatically cleared */ -sbit at 0xC5 P0IF; /* Port0 interrupt flag */ -sbit at 0xC7 STIF; /* Sleep Timer interrupt flag */ +sbit __at 0xC0 DMAIF; /* DMA complete interrupt flag */ +sbit __at 0xC1 T1IF; /* Timer 1 interrupt flag. Automatically cleared */ +sbit __at 0xC2 T2IF; /* Timer 2 interrupt flag. Automatically cleared */ +sbit __at 0xC3 T3IF; /* Timer 3 interrupt flag. Automatically cleared */ +sbit __at 0xC4 T4IF; /* Timer 4 interrupt flag. Automatically cleared */ +sbit __at 0xC5 P0IF; /* Port0 interrupt flag */ +sbit __at 0xC7 STIF; /* Sleep Timer interrupt flag */ #define IRCON_DMAIF (1 << 0) /* DMA complete interrupt flag */ #define IRCON_T1IF (1 << 1) /* Timer 1 interrupt flag. Automatically cleared */ @@ -190,15 +190,15 @@ sbit at 0xC7 STIF; /* Sleep Timer interrupt flag */ /* * IRCON2 */ -sfr at 0xE8 IRCON2; /* CPU Interrupt Flag 5 */ +sfr __at 0xE8 IRCON2; /* CPU Interrupt Flag 5 */ -sbit at 0xE8 USBIF; /* USB interrupt flag (shared with Port2) */ -sbit at 0xE8 P2IF; /* Port2 interrupt flag (shared with USB) */ -sbit at 0xE9 UTX0IF; /* USART0 TX interrupt flag */ -sbit at 0xEA UTX1IF; /* USART1 TX interrupt flag (shared with I2S TX) */ -sbit at 0xEA I2STXIF; /* I2S TX interrupt flag (shared with USART1 TX) */ -sbit at 0xEB P1IF; /* Port1 interrupt flag */ -sbit at 0xEC WDTIF; /* Watchdog timer interrupt flag */ +sbit __at 0xE8 USBIF; /* USB interrupt flag (shared with Port2) */ +sbit __at 0xE8 P2IF; /* Port2 interrupt flag (shared with USB) */ +sbit __at 0xE9 UTX0IF; /* USART0 TX interrupt flag */ +sbit __at 0xEA UTX1IF; /* USART1 TX interrupt flag (shared with I2S TX) */ +sbit __at 0xEA I2STXIF; /* I2S TX interrupt flag (shared with USART1 TX) */ +sbit __at 0xEB P1IF; /* Port1 interrupt flag */ +sbit __at 0xEC WDTIF; /* Watchdog timer interrupt flag */ #define IRCON2_USBIF (1 << 0) /* USB interrupt flag (shared with Port2) */ #define IRCON2_P2IF (1 << 0) /* Port2 interrupt flag (shared with USB) */ @@ -225,8 +225,8 @@ sbit at 0xEC WDTIF; /* Watchdog timer interrupt flag */ * Priority = (IP1 << 1) | IP0. Higher priority interrupts served first */ -sfr at 0xB9 IP1; /* Interrupt Priority 1 */ -sfr at 0xA9 IP0; /* Interrupt Priority 0 */ +sfr __at 0xB9 IP1; /* Interrupt Priority 1 */ +sfr __at 0xA9 IP0; /* Interrupt Priority 0 */ #define IP1_IPG5 (1 << 5) #define IP1_IPG4 (1 << 4) @@ -286,13 +286,13 @@ sfr at 0xA9 IP0; /* Interrupt Priority 0 */ */ /* Timer count */ -sfr at 0xCA T3CNT; -sfr at 0xEA T4CNT; +sfr __at 0xCA T3CNT; +sfr __at 0xEA T4CNT; /* Timer control */ -sfr at 0xCB T3CTL; -sfr at 0xEB T4CTL; +sfr __at 0xCB T3CTL; +sfr __at 0xEB T4CTL; #define TxCTL_DIV_1 (0 << 5) #define TxCTL_DIV_2 (1 << 5) @@ -312,10 +312,10 @@ sfr at 0xEB T4CTL; /* Timer 4 channel 0 compare control */ -sfr at 0xCC T3CCTL0; -sfr at 0xCE T3CCTL1; -sfr at 0xEC T4CCTL0; -sfr at 0xEE T4CCTL1; +sfr __at 0xCC T3CCTL0; +sfr __at 0xCE T3CCTL1; +sfr __at 0xEC T4CCTL0; +sfr __at 0xEE T4CCTL1; #define TxCCTLy_IM (1 << 6) #define TxCCTLy_CMP_SET (0 << 3) @@ -328,16 +328,16 @@ sfr at 0xEE T4CCTL1; #define TxCCTLy_CMP_MODE_ENABLE (1 << 2) /* Timer compare value */ -sfr at 0xCD T3CC0; -sfr at 0xCF T3CC1; -sfr at 0xED T4CC0; -sfr at 0xEF T4CC1; +sfr __at 0xCD T3CC0; +sfr __at 0xCF T3CC1; +sfr __at 0xED T4CC0; +sfr __at 0xEF T4CC1; /* * Peripheral control */ -sfr at 0xf1 PERCFG; +sfr __at 0xf1 PERCFG; #define PERCFG_T1CFG_ALT_1 (0 << 6) #define PERCFG_T1CFG_ALT_2 (1 << 6) #define PERCFG_T1CFG_ALT_MASK (1 << 6) |