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authorKeith Packard <keithp@keithp.com>2018-10-13 07:50:59 -0700
committerKeith Packard <keithp@keithp.com>2018-10-13 07:50:59 -0700
commit803c68d7933d03aaebda19786b63055d4a6d3d22 (patch)
tree6257a15fdb96f21ea9f860b8fc638bd7b082b1a0 /src
parente830d803d3e289f0f1a6d92ce208682af28d3f52 (diff)
altos/stm: Make flash loader work with either 8MHz or 16MHz xtal
Provide PLL definitions for both values. Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'src')
-rw-r--r--src/stm/ao_flash_stm_pins.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/stm/ao_flash_stm_pins.h b/src/stm/ao_flash_stm_pins.h
index d5893c80..b82046d7 100644
--- a/src/stm/ao_flash_stm_pins.h
+++ b/src/stm/ao_flash_stm_pins.h
@@ -21,6 +21,10 @@
#include <ao_flash_pins.h>
+#ifndef AO_PLLMUL
+
+#if AO_HSE == 8000000
+
/* PLLVCO = 96MHz (so that USB will work) */
#define AO_PLLMUL 12
#define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_12)
@@ -29,6 +33,22 @@
#define AO_PLLDIV 3
#define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_3)
+#endif
+
+#if AO_HSE == 16000000
+
+/* PLLVCO = 96MHz (so that USB will work) */
+#define AO_PLLMUL 6
+#define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_6)
+
+/* SYSCLK = 32MHz */
+#define AO_PLLDIV 3
+#define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_3)
+
+#endif
+
+#endif
+
/* HCLK = 32MHZ (CPU clock) */
#define AO_AHB_PRESCALER 1
#define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1