altos/stm32f4: Need to read-back register after clock enable

This was reported as necessary; I have no idea, but it's not
expensive, so why not...

Signed-off-by: Keith Packard <keithp@keithp.com>

1 files changed, 36 insertions, 2 deletions

diff --git a/src/stm32f4/stm32f4.h b/src/stm32f4/stm32f4.h
index dcdce667..3e8ec957 100644
--- a/src/stm32f4/stm32f4.h
+++ b/src/stm32f4/stm32f4.h
@@ -66,8 +66,8 @@ struct stm_rcc {
 	vuint32_t	pad_28;
 	vuint32_t	pad_2c;
 
-	vuint32_t	ahb1enr;
-	vuint32_t	ahb2enr;
+	vuint32_t	_ahb1enr;
+	vuint32_t	_ahb2enr;
 	vuint32_t	ahbdnr;
 	vuint32_t	pad_3c;
 
@@ -277,6 +277,38 @@ extern struct stm_rcc stm_rcc;
 #define  STM_RCC_DCKCFGR2_I2CFMP1SEL_HSI		2
 #define  STM_RCC_DCKCFGR2_I2CFMP1SEL_APB_ALSO		3
 
+static inline void
+stm_rcc_ahb1_clk_enable(uint32_t bit)
+{
+	stm_rcc._ahb1enr |= bit;
+	uint32_t value = stm_rcc._ahb1enr;
+	(void) value;
+}
+
+static inline void
+stm_rcc_ahb1_clk_disable(uint32_t bit)
+{
+	stm_rcc._ahb1enr &= ~bit;
+	uint32_t value = stm_rcc._ahb1enr;
+	(void) value;
+}
+
+static inline void
+stm_rcc_ahb2_clk_enable(uint32_t bit)
+{
+	stm_rcc._ahb2enr |= bit;
+	uint32_t value = stm_rcc._ahb2enr;
+	(void) value;
+}
+
+static inline void
+stm_rcc_ahb2_clk_disable(uint32_t bit)
+{
+	stm_rcc._ahb2enr &= ~bit;
+	uint32_t value = stm_rcc._ahb2enr;
+	(void) value;
+}
+
 struct stm_ictr {
 	vuint32_t	ictr;
 };
@@ -378,6 +410,8 @@ stm_nvic_get_priority(int irq) {
 
 #define isr(name) void stm_ ## name ## _isr(void)
 
+isr(halt);
+isr(ignore);
 isr(nmi);
 isr(hardfault);
 isr(memmanage);