diff options
| author | Keith Packard <keithp@keithp.com> | 2013-05-01 08:58:17 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2013-05-01 08:58:17 -0700 |
| commit | 1b773ba85f665cf4862683b1b66990655284a44a (patch) | |
| tree | c85dc194d250ceff7a249e1d7ba199107cb3ed57 /src/stm/ao_timer.c | |
| parent | fd16f97634cf74fcec001ce2e38ff262730f15a9 (diff) | |
altos: Use SYSTICK on STM32L
It's probably more power efficient than using one of the timers, and
it's certainly easier to configure.
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'src/stm/ao_timer.c')
| -rw-r--r-- | src/stm/ao_timer.c | 36 |
1 files changed, 9 insertions, 27 deletions
diff --git a/src/stm/ao_timer.c b/src/stm/ao_timer.c index ff477a03..daf2f400 100644 --- a/src/stm/ao_timer.c +++ b/src/stm/ao_timer.c @@ -36,10 +36,9 @@ volatile __data uint8_t ao_data_interval = 1; volatile __data uint8_t ao_data_count; #endif -void stm_tim6_isr(void) +void stm_systick_isr(void) { - if (stm_tim6.sr & (1 << STM_TIM67_SR_UIF)) { - stm_tim6.sr = 0; + if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) { ++ao_tick_count; #if HAS_TASK_QUEUE if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0) @@ -82,33 +81,16 @@ ao_timer_set_adc_interval(uint8_t interval) #define TIMER_10kHz ((AO_PCLK1 * TIMER_23467_SCALER) / 10000) +#define SYSTICK_RELOAD (AO_SYSTICK / 100 - 1) + void ao_timer_init(void) { - stm_nvic_set_enable(STM_ISR_TIM6_POS); - stm_nvic_set_priority(STM_ISR_TIM6_POS, AO_STM_NVIC_CLOCK_PRIORITY); - - /* Turn on timer 6 */ - stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM6EN); - - stm_tim6.psc = TIMER_10kHz; - stm_tim6.arr = 99; - stm_tim6.cnt = 0; - - /* Enable update interrupt */ - stm_tim6.dier = (1 << STM_TIM67_DIER_UIE); - - /* Poke timer to reload values */ - stm_tim6.egr |= (1 << STM_TIM67_EGR_UG); - - stm_tim6.cr2 = (STM_TIM67_CR2_MMS_RESET << STM_TIM67_CR2_MMS); - - /* And turn it on */ - stm_tim6.cr1 = ((0 << STM_TIM67_CR1_ARPE) | - (0 << STM_TIM67_CR1_OPM) | - (1 << STM_TIM67_CR1_URS) | - (0 << STM_TIM67_CR1_UDIS) | - (1 << STM_TIM67_CR1_CEN)); + stm_systick.rvr = SYSTICK_RELOAD; + stm_systick.cvr = 0; + stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) | + (1 << STM_SYSTICK_CSR_TICKINT) | + (STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE)); } #endif |