diff options
| author | Keith Packard <keithp@keithp.com> | 2013-01-13 20:48:47 -0800 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2013-01-13 20:54:14 -0800 |
| commit | 8d885616e2e522b8aea5e7d5398f16d330a0cffa (patch) | |
| tree | e3f40ac01c93c70f26d64604e4c97fbd7f32cdcd /src/stm/ao_spi_stm.c | |
| parent | f2810aa33fc6fe254761a0044c62c7b23e59e6bc (diff) | |
altos: Set STM GPIO output speed for SPI pins correctly
The GPIO pin settings affect the output impedence, and hence the
maximum speed for SPI. Cranking these to suitable values allows SPI to
run at full speed.
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'src/stm/ao_spi_stm.c')
| -rw-r--r-- | src/stm/ao_spi_stm.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/stm/ao_spi_stm.c b/src/stm/ao_spi_stm.c index 599d7ee0..7b4af964 100644 --- a/src/stm/ao_spi_stm.c +++ b/src/stm/ao_spi_stm.c @@ -425,12 +425,21 @@ ao_spi_init(void) #if HAS_SPI_1 # if SPI_1_PA5_PA6_PA7 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN); + stm_ospeedr_set(&stm_gpioa, 5, SPI_1_OSPEEDR); + stm_ospeedr_set(&stm_gpioa, 6, SPI_1_OSPEEDR); + stm_ospeedr_set(&stm_gpioa, 7, SPI_1_OSPEEDR); # endif # if SPI_1_PB3_PB4_PB5 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN); + stm_ospeedr_set(&stm_gpiob, 3, SPI_1_OSPEEDR); + stm_ospeedr_set(&stm_gpiob, 4, SPI_1_OSPEEDR); + stm_ospeedr_set(&stm_gpiob, 5, SPI_1_OSPEEDR); # endif # if SPI_1_PE13_PE14_PE15 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN); + stm_ospeedr_set(&stm_gpioe, 13, SPI_1_OSPEEDR); + stm_ospeedr_set(&stm_gpioe, 14, SPI_1_OSPEEDR); + stm_ospeedr_set(&stm_gpioe, 15, SPI_1_OSPEEDR); # endif stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SPI1EN); ao_spi_index[0] = AO_SPI_CONFIG_NONE; @@ -440,9 +449,15 @@ ao_spi_init(void) #if HAS_SPI_2 # if SPI_2_PB13_PB14_PB15 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN); + stm_ospeedr_set(&stm_gpiob, 13, SPI_2_OSPEEDR); + stm_ospeedr_set(&stm_gpiob, 14, SPI_2_OSPEEDR); + stm_ospeedr_set(&stm_gpiob, 15, SPI_2_OSPEEDR); # endif # if SPI_2_PD1_PD3_PD4 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN); + stm_ospeedr_set(&stm_gpiod, 1, SPI_2_OSPEEDR); + stm_ospeedr_set(&stm_gpiod, 3, SPI_2_OSPEEDR); + stm_ospeedr_set(&stm_gpiod, 4, SPI_2_OSPEEDR); # endif stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_SPI2EN); ao_spi_index[1] = AO_SPI_CONFIG_NONE; |