diff options
| author | Keith Packard <keithp@keithp.com> | 2012-04-09 22:17:33 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2012-04-09 22:17:33 -0700 |
| commit | 51aef5d4fc29986353ad887f4a67ed2fe35f8c8e (patch) | |
| tree | 537602d5a0ed6fdae7e4ce8830f3c24a4a87aca5 /src/stm-demo | |
| parent | 1dcfbb05531767e67df45c2799a2fe533834fb71 (diff) | |
altos: Make STM clock configuration per-product. Fix 32MHz CPU speed
This moves all of the STM clock configuration into ao_pins.h so that
each product can configure it separately. While doing this, I
discovered that the flash memory mode (64-bit, prefetch, latency 1)
wasn't actually getting set, which is why the CPU refused to work at
32MHz.
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'src/stm-demo')
| -rw-r--r-- | src/stm-demo/ao_pins.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/stm-demo/ao_pins.h b/src/stm-demo/ao_pins.h index 9fd1175d..3192c2b7 100644 --- a/src/stm-demo/ao_pins.h +++ b/src/stm-demo/ao_pins.h @@ -18,6 +18,23 @@ #ifndef _AO_PINS_H_ #define _AO_PINS_H_ +/* No external crystal */ +#define AO_HSE 0 + +#define AO_AHB_PRESCALER 1 +#define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1 + +#define AO_APB1_PRESCALER 2 +#define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE2_DIV_2 + +#define AO_APB2_PRESCALER 2 +#define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_2 + +#define AO_PLLMUL 6 +#define AO_PLLDIV 4 +#define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_6) +#define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_4) + #define HAS_SERIAL_1 1 #define USE_SERIAL_1_STDIN 1 #define SERIAL_1_PB6_PB7 1 |