diff options
| author | Keith Packard <keithp@keithp.com> | 2011-03-16 20:36:50 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-03-16 20:36:50 -0700 |
| commit | 82707a05af0eb2d54f46b58805c95cdf4e5a3703 (patch) | |
| tree | 917a1d0fd53eed822a84dcff74d1d5f2ce43791b /src/cc1111.h | |
| parent | 1d8579f973bfe1047ee91f03555e74abdc483e69 (diff) | |
altos: Internal flash ops block when running from flash
The docs say that if you are executing from flash, then the CPU will
stall after a flash write or erase command is started until the
operation is complete. Take advantage of that to simplify the flash
code.
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'src/cc1111.h')
| -rw-r--r-- | src/cc1111.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/cc1111.h b/src/cc1111.h index 20ed052a..effb1a68 100644 --- a/src/cc1111.h +++ b/src/cc1111.h @@ -884,6 +884,26 @@ __xdata __at (0xDFF9) volatile uint8_t U1DBUFXADDR; sfr at 0xc2 U0BAUD; sfr at 0xfa U1BAUD; +/* Flash controller */ + +sfr at 0xAE FCTL; +#define FCTL_BUSY (1 << 7) +#define FCTL_SWBSY (1 << 6) +#define FCTL_CONTRD_ENABLE (1 << 4) +#define FCTL_WRITE (1 << 1) +#define FCTL_ERASE (1 << 0) + +/* Flash write data. Write two bytes here */ +sfr at 0xAF FWDATA; +__xdata __at (0xDFAF) volatile uint8_t FWDATAXADDR; + +/* Flash write/erase address */ +sfr at 0xAD FADDRH; +sfr at 0xAC FADDRL; + +/* Flash timing */ +sfr at 0xAB FWT; + /* Radio */ sfr at 0xD9 RFD; |