Merge branch 'new-debian' into debian

Conflicts:
	ChangeLog
	debian/altos.install
	debian/changelog
	debian/control
	debian/copyright
	debian/dirs
	debian/docs
	debian/menu
	debian/rules
	src/Makefile

1 files changed, 77 insertions, 0 deletions

diff --git a/src/avr/ao_clock.c b/src/avr/ao_clock.c
new file mode 100644
index 00000000..0d42b6d5
--- /dev/null
+++ b/src/avr/ao_clock.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright © 2011 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#include "ao.h"
+
+/*
+ * AltOS always cranks the clock to the max frequency
+ */
+
+void
+ao_clock_init(void)
+{
+	/* disable RC clock */
+	CLKSEL0 &= ~(1 << RCE);
+
+	/* Disable PLL */
+	PLLCSR &= ~(1 << PLLE);
+
+	/* Enable external clock */
+	CLKSEL0 |= (1 << EXTE);
+
+	/* wait for external clock to be ready */
+	while ((CLKSTA & (1 << EXTON)) == 0)
+		;
+
+	/* select external clock */
+	CLKSEL0 |= (1 << CLKS);
+
+	/* Disable the clock prescaler */
+	cli();
+	CLKPR = (1 << CLKPCE);
+
+	/* Always run the system clock at 8MHz */
+#if AVR_CLOCK > 12000000UL
+	CLKPR = 1;
+#else
+	CLKPR = 0;
+#endif
+	sei();
+
+	/* Set up the PLL to use the crystal */
+
+	/* Use primary system clock as PLL source */
+	PLLFRQ = ((0 << PINMUX) |	/* Use primary clock */
+		  (0 << PLLUSB) |	/* No divide by 2 for USB */
+		  (0 << PLLTM0) |	/* Disable high speed timer */
+		  (0x4 << PDIV0));	/* 48MHz PLL clock */
+
+	/* Set the frequency of the crystal */
+#if AVR_CLOCK > 12000000UL
+	PLLCSR |= (1 << PINDIV);	/* For 16MHz crystal on Teensy board */
+#else
+	PLLCSR &= ~(1 << PINDIV);	/* For 8MHz crystal on TeleScience board */
+#endif
+
+	/* Enable the PLL */
+	PLLCSR |= (1 << PLLE);
+	while (!(PLLCSR & (1 << PLOCK)))
+		;
+
+	set_sleep_mode(SLEEP_MODE_IDLE);
+	sleep_enable();
+}