Initial AltOS import

author: Keith Packard <keithp@keithp.com> 2009-04-12 20:25:39 -0700
committer: Keith Packard <keithp@keithp.com> 2009-04-12 20:25:39 -0700
commit: 1903a86bf2cc6b685ccc475e62eabe49a4ec5b43 (patch)
tree: bc791a4a40f84ea8890e001c2d03afd1abd51d7d
9 files changed, 1270 insertions, 0 deletions
diff --git a/Makefile b/Makefile
new file mode 100644
index 00000000..2fb24898
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,59 @@
+PROG=altos
+CC=sdcc
+NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse \
+	--nolabelopt --nooverlay --peep-asm
+DEBUG=--debug
+
+CFLAGS=--model-large $(DEBUG) --less-pedantic \
+	--no-peep --int-long-reent --float-reent \
+
+LDFLAGS=--out-fmt-ihx
+LDFLAGS_RAM=$(LDFLAGS) --code-loc 0xf000 --code-size 0x800 \
+	--xram-loc 0xf800 --xram-size 0x700 --iram-size 0xff
+
+
+LDFLAGS_FLASH=$(LDFLAGS) --code-loc 0x0000 --code-size 0x8000 \
+	--xram-loc 0xf000 --xram-size 0xf00 --iram-size 0xff
+
+INC = \
+	ao.h \
+	cc1111.h
+
+SRC = \
+	ao_task.c \
+	ao_panic.c \
+	ao_test.c \
+	_bp.c
+	
+ADB=$(SRC:.c=.adb)
+ASM=$(SRC:.c=.asm)
+LNK=$(SRC:.c=.lnk)
+LST=$(SRC:.c=.lst)
+REL=$(SRC:.c=.rel)
+RST=$(SRC:.c=.rst)
+SYM=$(SRC:.c=.sym)
+
+PROGS=$(PROG)-flash.ihx $(PROG)-ram.ihx
+PCDB=$(PROGS:.ihx=.cdb)
+PLNK=$(PROGS:.ihx=.lnk)
+PMAP=$(PROGS:.ihx=.map)
+PMEM=$(PROGS:.ihx=.mem)
+PAOM=$(PROGS:.ihx=)
+
+%.rel : %.c $(INC)
+	$(CC) -c $(CFLAGS) -o$*.rel $*.c
+
+all: $(PROGS)
+
+$(PROG)-ram.ihx: $(REL) Makefile
+	$(CC) $(LDFLAGS_RAM) $(CFLAGS) -o $(PROG)-ram.ihx $(REL)
+	$(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o $(PROG)-flash.ihx $(REL)
+	sh check-stack ao.h $(PROG)-flash.mem
+
+$(PROG)-flash.ihx: $(PROG)-ram.ihx
+
+clean:
+	rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM)
+	rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM)
+
+install:
diff --git a/README b/README
new file mode 100644
index 00000000..83929a2a
--- /dev/null
+++ b/README
@@ -0,0 +1,32 @@
+AltOS - 8051 operating system for Altus-Metrum projects
+
+Parameters:
+
+ * Multi-tasking
+ * Non-preemptive
+ * Unix-style sleep/wakeup scheduling
+ * Strict round-robin, no priorities
+
+API:
+
+	int ao_sleep(void *wchan)
+
+		Puts current task to sleep. Will wake up when wchan is signalled
+	
+	int ao_wakeup(void *wchan)
+
+		Wakeup all tasks sleeping on wchan
+
+	void ao_add_task(struct ao_task *task)
+
+		Adds a task to the queue of available tasks
+
+	void ao_start_scheduler(void)
+
+		Invokes the scheduler, starting the operating system
+
+	void ao_switch(void)
+
+		Switches to another task which is ready to run. Allows
+		tasks which want to run for a while to give up the CPU
+		without needing to sleep
diff --git a/_bp.c b/_bp.c
new file mode 100644
index 00000000..a57b99bc
--- /dev/null
+++ b/_bp.c
@@ -0,0 +1,26 @@
+/*-------------------------------------------------------------------------
+
+  _bp.c :- just declares bp as a variable                
+
+             Written By -  Sandeep Dutta . sandeep.dutta@usa.net (1999)
+
+   This library is free software; you can redistribute it and/or modify it
+   under the terms of the GNU Library General Public License as published by the
+   Free Software Foundation; either version 2, or (at your option) any
+   later version.
+   
+   This library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU Library General Public License for more details.
+   
+   You should have received a copy of the GNU Library General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+   
+   In other words, you are welcome to use, share and improve this program.
+   You are forbidden to forbid anyone else to use, share and improve
+   what you give them.   Help stamp out software-hoarding!  
+-------------------------------------------------------------------------*/
+
+__data unsigned char bp ;
diff --git a/ao.h b/ao.h
new file mode 100644
index 00000000..dc2a0751
--- /dev/null
+++ b/ao.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2009 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#ifndef _AO_H_
+#define _AO_H_
+
+#include <stdint.h>
+#include <stdio.h>
+#include "cc1111.h"
+
+#define AO_STACK_START	0x11
+#define AO_STACK_END	0xfe
+#define AO_STACK_SIZE	(AO_STACK_END - AO_STACK_START + 1)
+
+struct ao_task {
+	__xdata void	*wchan;
+	uint8_t	stack[AO_STACK_SIZE];
+	uint8_t	stack_count;
+};
+
+#define AO_NUM_TASKS	10
+
+#define AO_ERROR_NO_TASK	1
+
+int ao_sleep(__xdata void *wchan);
+int ao_wakeup(__xdata void *wchan);
+void ao_add_task(__xdata struct ao_task * task, void (*start)(void));
+void ao_start_scheduler(void);
+void ao_yield(void) _naked;
+void ao_panic(uint8_t reason);
+
+#endif /* _AO_H_ */
diff --git a/ao_panic.c b/ao_panic.c
new file mode 100644
index 00000000..9f9167d8
--- /dev/null
+++ b/ao_panic.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright © 2009 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#include "ao.h"
+
+void
+ao_panic(uint8_t reason)
+{
+	(void) reason;
+	for (;;)
+		;
+}
diff --git a/ao_task.c b/ao_task.c
new file mode 100644
index 00000000..4f7387e3
--- /dev/null
+++ b/ao_task.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright © 2009 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#include "ao.h"
+
+#define AO_NO_TASK	0xff
+
+__xdata struct ao_task * __xdata ao_tasks[AO_NUM_TASKS];
+__data uint8_t ao_num_tasks;
+__data uint8_t ao_cur_task_id;
+__xdata struct ao_task *__data ao_cur_task;
+
+void
+ao_add_task(__xdata struct ao_task * task, void (*start)(void))
+{
+	uint8_t	__xdata *stack;
+	if (ao_num_tasks == AO_NUM_TASKS)
+		ao_panic(AO_ERROR_NO_TASK);
+	ao_tasks[ao_num_tasks++] = task;
+	/*
+	 * Construct a stack frame so that it will 'return'
+	 * to the start of the task
+	 */
+	stack = task->stack;
+	
+	*stack++ = ((uint16_t) start);
+	*stack++ = ((uint16_t) start) >> 8;
+	
+	/* and the stuff saved by ao_switch */
+	*stack++ = 0;		/* acc */
+	*stack++ = 0x80;	/* IE */
+	*stack++ = 0;		/* DPL */
+	*stack++ = 0;		/* DPH */
+	*stack++ = 0;		/* B */
+	*stack++ = 0;		/* R2 */
+	*stack++ = 0;		/* R3 */
+	*stack++ = 0;		/* R4 */
+	*stack++ = 0;		/* R5 */
+	*stack++ = 0;		/* R6 */
+	*stack++ = 0;		/* R7 */
+	*stack++ = 0;		/* R0 */
+	*stack++ = 0;		/* R1 */
+	*stack++ = 0;		/* PSW */
+	*stack++ = 0;		/* BP */
+	task->stack_count = stack - task->stack;
+	task->wchan = NULL;
+}
+
+/* Task switching function. This must not use any stack variables */
+void
+ao_yield(void) _naked
+{
+	static uint8_t __data stack_len;
+	static __data uint8_t * __data stack_ptr;
+	static __xdata uint8_t * __data save_ptr;
+
+	/* Save current context */
+	_asm
+		/* Push ACC first, as when restoring the context it must be restored
+		 * last (it is used to set the IE register). */
+		push	ACC
+		/* Store the IE register then disable interrupts. */
+		push	_IEN0
+		clr	_EA
+		push	DPL
+		push	DPH
+		push	b
+		push	ar2
+		push	ar3
+		push	ar4
+		push	ar5
+		push	ar6
+		push	ar7
+		push	ar0
+		push	ar1
+		push	PSW
+	_endasm;
+	PSW = 0;
+	_asm
+		push	_bp
+	_endasm;
+	
+	if (ao_cur_task_id != AO_NO_TASK)
+	{
+		/* Save the current stack */
+		stack_len = SP - AO_STACK_START;
+		ao_cur_task->stack_count = stack_len;
+		stack_ptr = (uint8_t __data *) AO_STACK_START;
+		save_ptr = (uint8_t __xdata *) ao_cur_task->stack;
+		while (stack_len--)
+			*save_ptr++ = *stack_ptr++;
+	}
+	
+	/* Empty the stack; might as well let interrupts have the whole thing */
+	SP = AO_STACK_START;
+
+	/* Find a task to run. If there isn't any runnable task,
+	 * this loop will run forever, which is just fine
+	 */
+	for (;;) {
+		++ao_cur_task_id;
+		if (ao_cur_task_id == ao_num_tasks)
+			ao_cur_task_id = 0;
+		ao_cur_task = ao_tasks[ao_cur_task_id];
+		if (ao_cur_task->wchan == NULL)
+			break;
+	}
+
+	/* Restore the old stack */
+	stack_len = ao_cur_task->stack_count;
+	stack_ptr = (uint8_t __data *) AO_STACK_START;
+	save_ptr = (uint8_t __xdata *) ao_cur_task->stack;
+	while (stack_len--)
+		*stack_ptr++ = *save_ptr++;
+	SP = (uint8_t) (stack_ptr - 1);
+
+	_asm
+		pop		_bp
+		pop		PSW
+		pop		ar1
+		pop		ar0
+		pop		ar7
+		pop		ar6
+		pop		ar5
+		pop		ar4
+		pop		ar3
+		pop		ar2
+		pop		b
+		pop		DPH
+		pop		DPL
+		/* The next byte of the stack is the IE register.  Only the global
+		enable bit forms part of the task context.  Pop off the IE then set
+		the global enable bit to match that of the stored IE register. */
+		pop		ACC
+		JB		ACC.7,0098$
+		CLR		_EA
+		LJMP	0099$
+	0098$:
+		SETB		_EA
+	0099$:
+		/* Finally pop off the ACC, which was the first register saved. */
+		pop		ACC
+		ret
+	_endasm;
+}
+
+int
+ao_sleep(__xdata void *wchan)
+{
+	ao_cur_task->wchan = wchan;
+	ao_yield();
+}
+
+int
+ao_wakeup(__xdata void *wchan)
+{
+	uint8_t	i;
+
+	for (i = 0; i < ao_num_tasks; i++)
+		if (ao_tasks[i]->wchan == wchan)
+			ao_tasks[i]->wchan = NULL;
+}
+
+void
+ao_start_scheduler(void)
+{
+	ao_cur_task_id = AO_NO_TASK;
+	ao_cur_task = NULL;
+	ao_yield();
+}
diff --git a/ao_test.c b/ao_test.c
new file mode 100644
index 00000000..8852308e
--- /dev/null
+++ b/ao_test.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2009 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#include "ao.h"
+
+struct ao_task __xdata blink_task;
+
+void delay(int n) __reentrant
+{
+	while (n--)
+		ao_yield();
+}
+
+void
+blink(void)
+{
+	for (;;) {
+		P1 ^= 2;
+		delay(100);
+	}
+}
+
+void
+main(void)
+{
+	CLKCON = 0;
+	/* Set p1_1 to output */
+	P1DIR = 0x02;
+	
+	ao_add_task(&blink_task, blink);
+	ao_start_scheduler();
+}
diff --git a/cc1111.h b/cc1111.h
new file mode 100644
index 00000000..58f6daa3
--- /dev/null
+++ b/cc1111.h
@@ -0,0 +1,834 @@
+/*-------------------------------------------------------------------------
+   Register Declarations for the ChipCon CC1111 Processor Range
+
+   Copyright © 2008 Keith Packard <keithp@keithp.com>
+  
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+  
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+  
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+   Adapted from the Cygnal C8051F12x config file which is:
+ 
+   Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl
+
+   This library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   This library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with this library; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+-------------------------------------------------------------------------*/
+
+#ifndef _CC1111_H_
+#define _CC1111_H_
+#include <cc1110.h>
+#include <stdint.h>
+
+sfr at 0xA8 IEN0;		/* Interrupt Enable 0 Register */
+
+sbit at 0xA8 RFTXRXIE;		/* RF TX/RX done interrupt enable */
+sbit at 0xA9 ADCIE;		/* ADC interrupt enable */
+sbit at 0xAA URX0IE;		/* USART0 RX interrupt enable */
+sbit at 0xAB URX1IE;		/* USART1 RX interrupt enable (shared with I2S RX) */
+sbit at 0xAB I2SRXIE;		/* I2S RX interrupt enable (shared with USART1 RX) */
+sbit at 0xAC ENCIE;		/* AES encryption/decryption interrupt enable */
+sbit at 0xAD STIE;		/* Sleep Timer interrupt enable */
+sbit at 0xAF EA;		/* Enable All */
+
+#define IEN0_EA			(1 << 7)
+#define IEN0_STIE		(1 << 5)
+#define IEN0_ENCIE		(1 << 4)
+#define IEN0_URX1IE		(1 << 3)
+#define IEN0_I2SRXIE		(1 << 3)
+#define IEN0_URX0IE		(1 << 2)
+#define IEN0_ADCIE		(1 << 1)
+#define IEN0_RFTXRXIE		(1 << 0)
+
+sfr at 0xB8 IEN1;		/* Interrupt Enable 1 Register */
+
+#define IEN1_P0IE		(1 << 5)	/* Port 0 interrupt enable */
+#define IEN1_T4IE		(1 << 4)	/* Timer 4 interrupt enable */
+#define IEN1_T3IE		(1 << 3)	/* Timer 3 interrupt enable */
+#define IEN1_T2IE		(1 << 2)	/* Timer 2 interrupt enable */
+#define IEN1_T1IE		(1 << 1)	/* Timer 1 interrupt enable */
+#define IEN1_DMAIE		(1 << 0)	/* DMA transfer interrupt enable */
+
+/* IEN2 */
+sfr at 0x9A IEN2;		/* Interrupt Enable 2 Register */
+
+#define IEN2_WDTIE		(1 << 5)	/* Watchdog timer interrupt enable */
+#define IEN2_P1IE		(1 << 4)	/* Port 1 interrupt enable */
+#define IEN2_UTX1IE		(1 << 3)	/* USART1 TX interrupt enable */
+#define IEN2_I2STXIE		(1 << 3)	/* I2S TX interrupt enable */
+#define IEN2_UTX0IE		(1 << 2)	/* USART0 TX interrupt enable */
+#define IEN2_P2IE		(1 << 1)	/* Port 2 interrupt enable */
+#define IEN2_USBIE		(1 << 1)	/* USB interrupt enable */
+#define IEN2_RFIE		(1 << 0)	/* RF general interrupt enable */
+
+/* SLEEP 0xBE */
+#define SLEEP_USB_EN		(1 << 7)
+#define SLEEP_XOSC_STB		(1 << 6)
+#define SLEEP_HFRC_STB		(1 << 5)
+#define SLEEP_RST_POWER		(0 << 3)
+#define SLEEP_RST_EXTERNAL	(1 << 3)
+#define SLEEP_RST_WATCHDOG	(2 << 3)
+#define SLEEP_RST_MASK		(3 << 3)
+#define SLEEP_OSC_PD		(1 << 2)
+#define SLEEP_MODE_PM0		(0 << 0)
+#define SLEEP_MODE_PM1		(1 << 0)
+#define SLEEP_MODE_PM2		(2 << 0)
+#define SLEEP_MODE_PM3		(3 << 0)
+#define SLEEP_MODE_MASK		(3 << 0)
+
+/*
+ * TCON
+ */
+sfr at 0x88 TCON;	/* CPU Interrupt Flag 1 */
+
+sbit at 0x8F URX1IF;	/* USART1 RX interrupt flag. Automatically cleared */
+sbit at 0x8F I2SRXIF;	/* I2S RX interrupt flag. Automatically cleared */
+sbit at 0x8D ADCIF;	/* ADC interrupt flag. Automatically cleared */
+sbit at 0x8B URX0IF;	/* USART0 RX interrupt flag. Automatically cleared */
+sbit at 0x89 RFTXRXIF;	/* RF TX/RX complete interrupt flag. Automatically cleared */
+
+#define TCON_URX1IF	(1 << 7)
+#define TCON_I2SRXIF	(1 << 7)
+#define TCON_ADCIF	(1 << 5)
+#define TCON_URX0IF	(1 << 3)
+#define TCON_RFTXRXIF	(1 << 1)
+
+/*
+ * S0CON
+ */
+sfr at 0x98 S0CON;	/* CPU Interrupt Flag 2 */
+
+sbit at 0x98 ENCIF_0;	/* AES interrupt 0. */
+sbit at 0x99 ENCIF_1;	/* AES interrupt 1. */
+
+#define S0CON_ENCIF_1	(1 << 1)
+#define S0CON_ENCIF_0	(1 << 0)
+
+/* 
+ * S1CON
+ */
+sfr at 0x9B S1CON;	/* CPU Interrupt Flag 3 */
+
+#define S1CON_RFIF_1	(1 << 1)
+#define S1CON_RFIF_0	(1 << 0)
+
+/*
+ * IRCON
+ */
+sfr at 0xC0 IRCON;	/* CPU Interrupt Flag 4 */
+
+sbit at 0xC0 DMAIF;	/* DMA complete interrupt flag */
+sbit at 0xC1 T1IF;	/* Timer 1 interrupt flag. Automatically cleared */
+sbit at 0xC2 T2IF;	/* Timer 2 interrupt flag. Automatically cleared */
+sbit at 0xC3 T3IF;	/* Timer 3 interrupt flag. Automatically cleared */
+sbit at 0xC4 T4IF;	/* Timer 4 interrupt flag. Automatically cleared */
+sbit at 0xC5 P0IF;	/* Port0 interrupt flag */
+sbit at 0xC7 STIF;	/* Sleep Timer interrupt flag */
+
+#define IRCON_DMAIF	(1 << 0)	/* DMA complete interrupt flag */
+#define IRCON_T1IF	(1 << 1)	/* Timer 1 interrupt flag. Automatically cleared */
+#define IRCON_T2IF	(1 << 2)	/* Timer 2 interrupt flag. Automatically cleared */
+#define IRCON_T3IF	(1 << 3)	/* Timer 3 interrupt flag. Automatically cleared */
+#define IRCON_T4IF	(1 << 4)	/* Timer 4 interrupt flag. Automatically cleared */
+#define IRCON_P0IF	(1 << 5)	/* Port0 interrupt flag */
+#define IRCON_STIF	(1 << 7)	/* Sleep Timer interrupt flag */
+
+/*
+ * IRCON2
+ */
+sfr at 0xE8 IRCON2;	/* CPU Interrupt Flag 5 */
+
+sbit at 0xE8 USBIF;	/* USB interrupt flag (shared with Port2) */
+sbit at 0xE8 P2IF;	/* Port2 interrupt flag (shared with USB) */
+sbit at 0xE9 UTX0IF;	/* USART0 TX interrupt flag */
+sbit at 0xEA UTX1IF;	/* USART1 TX interrupt flag (shared with I2S TX) */
+sbit at 0xEA I2STXIF;	/* I2S TX interrupt flag (shared with USART1 TX) */
+sbit at 0xEB P1IF;	/* Port1 interrupt flag */
+sbit at 0xEC WDTIF;	/* Watchdog timer interrupt flag */
+
+#define IRCON2_USBIF	(1 << 0)	/* USB interrupt flag (shared with Port2) */
+#define IRCON2_P2IF	(1 << 0)	/* Port2 interrupt flag (shared with USB) */
+#define IRCON2_UTX0IF	(1 << 1)	/* USART0 TX interrupt flag */
+#define IRCON2_UTX1IF	(1 << 2)	/* USART1 TX interrupt flag (shared with I2S TX) */
+#define IRCON2_I2STXIF	(1 << 2)	/* I2S TX interrupt flag (shared with USART1 TX) */
+#define IRCON2_P1IF	(1 << 3)	/* Port1 interrupt flag */
+#define IRCON2_WDTIF	(1 << 4)	/* Watchdog timer interrupt flag */
+
+/*
+ * IP1 - Interrupt Priority 1
+ */
+
+/*
+ * Interrupt priority groups:
+ *
+ * IPG0		RFTXRX		RF		DMA
+ * IPG1		ADC		T1		P2INT/USB
+ * IPG2		URX0		T2		UTX0
+ * IPG3		URX1/I2SRX	T3		UTX1 / I2STX
+ * IPG4		ENC		T4		P1INT
+ * IPG5		ST		P0INT		WDT
+ *
+ * Priority = (IP1 << 1) | IP0. Higher priority interrupts served first
+ */
+
+sfr at 0xB9 IP1;	/* Interrupt Priority 1 */
+sfr at 0xA9 IP0;	/* Interrupt Priority 0 */
+
+#define IP1_IPG5	(1 << 5)
+#define IP1_IPG4	(1 << 4)
+#define IP1_IPG3	(1 << 3)
+#define IP1_IPG2	(1 << 2)
+#define IP1_IPG1	(1 << 1)
+#define IP1_IPG0	(1 << 0)
+
+#define IP0_IPG5	(1 << 5)
+#define IP0_IPG4	(1 << 4)
+#define IP0_IPG3	(1 << 3)
+#define IP0_IPG2	(1 << 2)
+#define IP0_IPG1	(1 << 1)
+#define IP0_IPG0	(1 << 0)
+
+/*
+ * Timer 1
+ */
+#define T1CTL_MODE_SUSPENDED	(0 << 0)
+#define T1CTL_MODE_FREE		(1 << 0)
+#define T1CTL_MODE_MODULO	(2 << 0)
+#define T1CTL_MODE_UP_DOWN	(3 << 0)
+#define T1CTL_MODE_MASK		(3 << 0)
+#define T1CTL_DIV_1		(0 << 2)
+#define T1CTL_DIV_8		(1 << 2)
+#define T1CTL_DIV_32		(2 << 2)
+#define T1CTL_DIV_128		(3 << 2)
+#define T1CTL_DIV_MASK		(3 << 2)
+#define T1CTL_OVFIF		(1 << 4)
+#define T1CTL_CH0IF		(1 << 5)
+#define T1CTL_CH1IF		(1 << 6)
+#define T1CTL_CH2IF		(1 << 7)
+
+#define T1CCTL_NO_CAPTURE	(0 << 0)
+#define T1CCTL_CAPTURE_RISING	(1 << 0)
+#define T1CCTL_CAPTURE_FALLING	(2 << 0)
+#define T1CCTL_CAPTURE_BOTH	(3 << 0)
+#define T1CCTL_CAPTURE_MASK	(3 << 0)
+
+#define T1CCTL_MODE_CAPTURE	(0 << 2)
+#define T1CCTL_MODE_COMPARE	(1 << 2)
+
+#define T1CTL_CMP_SET		(0 << 3)
+#define T1CTL_CMP_CLEAR		(1 << 3)
+#define T1CTL_CMP_TOGGLE	(2 << 3)
+#define T1CTL_CMP_SET_CLEAR	(3 << 3)
+#define T1CTL_CMP_CLEAR_SET	(4 << 3)
+
+#define T1CTL_IM_DISABLED	(0 << 6)
+#define T1CTL_IM_ENABLED	(1 << 6)
+
+#define T1CTL_CPSEL_NORMAL	(0 << 7)
+#define T1CTL_CPSEL_RF		(1 << 7)
+
+/*
+ * Timer 3 and Timer 4
+ */
+
+/* Timer count */
+sfr at 0xCA T3CNT;
+sfr at 0xEA T4CNT;
+
+/* Timer control */
+ 
+sfr at 0xCB T3CTL;
+sfr at 0xEB T4CTL;
+
+#define TxCTL_DIV_1		(0 << 5)
+#define TxCTL_DIV_2		(1 << 5)
+#define TxCTL_DIV_4		(2 << 5)
+#define TxCTL_DIV_8		(3 << 5)
+#define TxCTL_DIV_16		(4 << 5)
+#define TxCTL_DIV_32		(5 << 5)
+#define TxCTL_DIV_64		(6 << 5)
+#define TxCTL_DIV_128		(7 << 5)
+#define TxCTL_START		(1 << 4)
+#define TxCTL_OVFIM		(1 << 3)
+#define TxCTL_CLR		(1 << 2)
+#define TxCTL_MODE_FREE		(0 << 0)
+#define TxCTL_MODE_DOWN		(1 << 0)
+#define TxCTL_MODE_MODULO	(2 << 0)
+#define TxCTL_MODE_UP_DOWN	(3 << 0)
+
+/* Timer 4 channel 0 compare control */
+
+sfr at 0xCC T3CCTL0;
+sfr at 0xCE T3CCTL1;
+sfr at 0xEC T4CCTL0;
+sfr at 0xEE T4CCTL1;
+
+#define TxCCTLy_IM			(1 << 6)
+#define TxCCTLy_CMP_SET			(0 << 3)
+#define TxCCTLy_CMP_CLEAR		(1 << 3)
+#define TxCCTLy_CMP_TOGGLE		(2 << 3)
+#define TxCCTLy_CMP_SET_UP_CLEAR_DOWN	(3 << 3)
+#define TxCCTLy_CMP_CLEAR_UP_SET_DOWN	(4 << 3)
+#define TxCCTLy_CMP_SET_CLEAR_FF	(5 << 3)
+#define TxCCTLy_CMP_CLEAR_SET_00	(6 << 3)
+#define TxCCTLy_CMP_MODE_ENABLE		(1 << 2)
+
+/* Timer compare value */
+sfr at 0xCD T3CC0;
+sfr at 0xCF T3CC1;
+sfr at 0xED T4CC0;
+sfr at 0xEF T4CC1;
+
+/*
+ * Peripheral control
+ */
+
+sfr at 0xf1 PERCFG;
+#define PERCFG_T1CFG_ALT_1      (0 << 6)
+#define PERCFG_T1CFG_ALT_2      (1 << 6)
+#define PERCFG_T1CFG_ALT_MASK   (1 << 6)
+
+#define PERCFG_T3CFG_ALT_1      (0 << 5)
+#define PERCFG_T3CFG_ALT_2      (1 << 5)
+#define PERCFG_T3CFG_ALT_MASK   (1 << 5)
+
+#define PERCFG_T4CFG_ALT_1      (0 << 4)
+#define PERCFG_T4CFG_ALT_2      (1 << 4)
+#define PERCFG_T4CFG_ALT_MASK   (1 << 4)
+
+#define PERCFG_U1CFG_ALT_1      (0 << 1)
+#define PERCFG_U1CFG_ALT_2      (1 << 1)
+#define PERCFG_U1CFG_ALT_MASK   (1 << 1)
+
+#define PERCFG_U0CFG_ALT_1      (0 << 0)
+#define PERCFG_U0CFG_ALT_2      (1 << 0)
+#define PERCFG_U0CFG_ALT_MASK   (1 << 0)
+
+/* directly addressed USB registers */
+__xdata __at (0xde00) volatile uint8_t USBADDR;
+__xdata __at (0xde01) volatile uint8_t USBPOW;
+__xdata __at (0xde02) volatile uint8_t USBIIF;
+
+__xdata __at (0xde04) volatile uint8_t USBOIF;
+
+__xdata __at (0xde06) volatile uint8_t USBCIF;
+__xdata __at (0xde07) volatile uint8_t USBIIE;
+
+__xdata __at (0xde09) volatile uint8_t USBOIE;
+
+__xdata __at (0xde0b) volatile uint8_t USBCIE;
+
+# define USBCIE_SOFIE		(1 << 3)
+# define USBCIE_RSTIE		(1 << 2)
+# define USBCIE_RESUMEIE	(1 << 1)
+# define USBCIE_SUSPENDIE	(1 << 0)
+
+__xdata __at (0xde0c) volatile uint8_t USBFRML;
+__xdata __at (0xde0d) volatile uint8_t USBFRMH;
+__xdata __at (0xde0e) volatile uint8_t USBINDEX;
+
+/* indexed USB registers, must set USBINDEX to 0-5 */
+__xdata __at (0xde10) volatile uint8_t USBMAXI;
+__xdata __at (0xde11) volatile uint8_t USBCS0;
+
+# define USBCS0_CLR_SETUP_END		(1 << 7)
+# define USBCS0_CLR_OUTPKT_RDY		(1 << 6)
+# define USBCS0_SEND_STALL		(1 << 5)
+# define USBCS0_SETUP_END		(1 << 4)
+# define USBCS0_DATA_END		(1 << 3)
+# define USBCS0_SENT_STALL		(1 << 2)
+# define USBCS0_INPKT_RDY		(1 << 1)
+# define USBCS0_OUTPKT_RDY		(1 << 0)
+
+__xdata __at (0xde11) volatile uint8_t USBCSIL;
+
+# define USBCSIL_CLR_DATA_TOG		(1 << 6)
+# define USBCSIL_SENT_STALL		(1 << 5)
+# define USBCSIL_SEND_STALL		(1 << 4)
+# define USBCSIL_FLUSH_PACKET		(1 << 3)
+# define USBCSIL_UNDERRUN		(1 << 2)
+# define USBCSIL_PKT_PRESENT		(1 << 1)
+# define USBCSIL_INPKT_RDY		(1 << 0)
+
+__xdata __at (0xde12) volatile uint8_t USBCSIH;
+
+# define USBCSIH_AUTOSET		(1 << 7)
+# define USBCSIH_ISO			(1 << 6)
+# define USBCSIH_FORCE_DATA_TOG		(1 << 3)
+# define USBCSIH_IN_DBL_BUF		(1 << 0)
+
+__xdata __at (0xde13) volatile uint8_t USBMAXO;
+__xdata __at (0xde14) volatile uint8_t USBCSOL;
+
+# define USBCSOL_CLR_DATA_TOG		(1 << 7)
+# define USBCSOL_SENT_STALL		(1 << 6)
+# define USBCSOL_SEND_STALL		(1 << 5)
+# define USBCSOL_FLUSH_PACKET		(1 << 4)
+# define USBCSOL_DATA_ERROR		(1 << 3)
+# define USBCSOL_OVERRUN		(1 << 2)
+# define USBCSOL_FIFO_FULL		(1 << 1)
+# define USBCSOL_OUTPKT_RDY		(1 << 0)
+
+__xdata __at (0xde15) volatile uint8_t USBCSOH;
+
+# define USBCSOH_AUTOCLEAR		(1 << 7)
+# define USBCSOH_ISO			(1 << 6)
+# define USBCSOH_OUT_DBL_BUF		(1 << 0)
+
+__xdata __at (0xde16) volatile uint8_t USBCNT0;
+__xdata __at (0xde16) volatile uint8_t USBCNTL;
+__xdata __at (0xde17) volatile uint8_t USBCNTH;
+
+__xdata __at (0xde20) volatile uint8_t USBFIFO[12];
+
+/* ADC Data register, low and high */
+sfr at 0xBA ADCL;
+sfr at 0xBB ADCH;
+__xdata __at (0xDFBA) volatile uint16_t ADCXDATA;
+
+/* ADC Control Register 1 */
+sfr at 0xB4 ADCCON1;
+
+# define ADCCON1_EOC		(1 << 7)	/* conversion complete */
+# define ADCCON1_ST		(1 << 6)	/* start conversion */
+
+# define ADCCON1_STSEL_MASK	(3 << 4)	/* start select */
+# define ADCCON1_STSEL_EXTERNAL	(0 << 4)	/* P2_0 pin triggers */
+# define ADCCON1_STSEL_FULLSPEED (1 << 4)	/* full speed, no waiting */
+# define ADCCON1_STSEL_TIMER1	(2 << 4)	/* timer 1 channel 0 */
+# define ADCCON1_STSEL_START	(3 << 4)	/* set start bit */
+
+# define ADCCON1_RCTRL_MASK	(3 << 2)	/* random number control */
+# define ADCCON1_RCTRL_COMPLETE	(0 << 2)	/* operation completed */
+# define ADCCON1_RCTRL_CLOCK_LFSR (1 << 2)	/* Clock the LFSR once */
+
+/* ADC Control Register 2 */
+sfr at 0xB5 ADCCON2;
+
+# define ADCCON2_SREF_MASK	(3 << 6)	/* reference voltage */
+# define ADCCON2_SREF_1_25V	(0 << 6)	/* internal 1.25V */
+# define ADCCON2_SREF_EXTERNAL	(1 << 6)	/* external on AIN7 cc1110 */
+# define ADCCON2_SREF_VDD	(2 << 6)	/* VDD on the AVDD pin */
+# define ADCCON2_SREF_EXTERNAL_DIFF (3 << 6)	/* external on AIN6-7 cc1110 */
+
+# define ADCCON2_SDIV_MASK	(3 << 4)	/* decimation rate */
+# define ADCCON2_SDIV_64	(0 << 4)	/* 7 bits */
+# define ADCCON2_SDIV_128	(1 << 4)	/* 9 bits */
+# define ADCCON2_SDIV_256	(2 << 4)	/* 10 bits */
+# define ADCCON2_SDIV_512	(3 << 4)	/* 12 bits */
+
+# define ADCCON2_SCH_MASK	(0xf << 0)	/* Sequence channel select */
+# define ADCCON2_SCH_SHIFT	0
+# define ADCCON2_SCH_AIN0	(0 << 0)
+# define ADCCON2_SCH_AIN1	(1 << 0)
+# define ADCCON2_SCH_AIN2	(2 << 0)
+# define ADCCON2_SCH_AIN3	(3 << 0)
+# define ADCCON2_SCH_AIN4	(4 << 0)
+# define ADCCON2_SCH_AIN5	(5 << 0)
+# define ADCCON2_SCH_AIN6	(6 << 0)
+# define ADCCON2_SCH_AIN7	(7 << 0)
+# define ADCCON2_SCH_AIN0_AIN1	(8 << 0)
+# define ADCCON2_SCH_AIN2_AIN3	(9 << 0)
+# define ADCCON2_SCH_AIN4_AIN5	(0xa << 0)
+# define ADCCON2_SCH_AIN6_AIN7	(0xb << 0)
+# define ADCCON2_SCH_GND	(0xc << 0)
+# define ADCCON2_SCH_VREF	(0xd << 0)
+# define ADCCON2_SCH_TEMP	(0xe << 0)
+# define ADCCON2_SCH_VDD_3	(0xf << 0)
+
+
+/* ADC Control Register 3 */
+sfr at 0xB6 ADCCON3;
+
+# define ADCCON3_EREF_MASK	(3 << 6)	/* extra conversion reference */
+# define ADCCON3_EREF_1_25	(0 << 6)	/* internal 1.25V */
+# define ADCCON3_EREF_EXTERNAL	(1 << 6)	/* external AIN7 cc1110 */
+# define ADCCON3_EREF_VDD	(2 << 6)	/* VDD on the AVDD pin */
+# define ADCCON3_EREF_EXTERNAL_DIFF (3 << 6)	/* external AIN6-7 cc1110 */
+# define ADCCON3_EDIV_MASK	(3 << 4)	/* extral decimation */
+# define ADCCON3_EDIV_64	(0 << 4)	/* 7 bits */
+# define ADCCON3_EDIV_128	(1 << 4)	/* 9 bits */
+# define ADCCON3_EDIV_256	(2 << 4)	/* 10 bits */
+# define ADCCON3_EDIV_512	(3 << 4)	/* 12 bits */
+# define ADCCON3_ECH_MASK	(0xf << 0)	/* Sequence channel select */
+# define ADCCON3_ECH_SHIFT	0
+# define ADCCON3_ECH_AIN0	(0 << 0)
+# define ADCCON3_ECH_AIN1	(1 << 0)
+# define ADCCON3_ECH_AIN2	(2 << 0)
+# define ADCCON3_ECH_AIN3	(3 << 0)
+# define ADCCON3_ECH_AIN4	(4 << 0)
+# define ADCCON3_ECH_AIN5	(5 << 0)
+# define ADCCON3_ECH_AIN6	(6 << 0)
+# define ADCCON3_ECH_AIN7	(7 << 0)
+# define ADCCON3_ECH_AIN0_AIN1	(8 << 0)
+# define ADCCON3_ECH_AIN2_AIN3	(9 << 0)
+# define ADCCON3_ECH_AIN4_AIN5	(0xa << 0)
+# define ADCCON3_ECH_AIN6_AIN7	(0xb << 0)
+# define ADCCON3_ECH_GND	(0xc << 0)
+# define ADCCON3_ECH_VREF	(0xd << 0)
+# define ADCCON3_ECH_TEMP	(0xe << 0)
+# define ADCCON3_ECH_VDD_3	(0xf << 0)
+
+/*
+ * ADC configuration register, this selects which
+ * GPIO pins are to be used as ADC inputs
+ */
+sfr at 0xF2 ADCCFG;
+
+/*
+ * Pin selectors, these set which pins are
+ * using their peripheral function
+ */
+sfr at 0xF3 P0SEL;
+sfr at 0xF4 P1SEL;
+sfr at 0xF5 P2SEL;
+
+#define P2SEL_PRI3P1_USART0		(0 << 6)
+#define P2SEL_PRI3P1_USART1		(1 << 6)
+#define P2SEL_PRI3P1_MASK		(1 << 6)
+#define P2SEL_PRI2P1_USART1		(0 << 5)
+#define P2SEL_PRI2P1_TIMER3		(1 << 5)
+#define P2SEL_PRI1P1_TIMER1		(0 << 4)
+#define P2SEL_PRI1P1_TIMER4		(1 << 4)
+#define P2SEL_PRI0P1_USART0		(0 << 3)
+#define P2SEL_PRI0P1_TIMER1		(1 << 3)
+#define P2SEL_SELP2_4_GPIO		(0 << 2)
+#define P2SEL_SELP2_4_PERIPHERAL	(1 << 2)
+#define P2SEL_SELP2_3_GPIO		(0 << 1)
+#define P2SEL_SELP2_3_PERIPHERAL	(1 << 1)
+#define P2SEL_SELP2_0_GPIO		(0 << 0)
+#define P2SEL_SELP2_0_PERIPHERAL	(1 << 0)
+#define P2SEL_SELP2_0_MASK		(1 << 0)
+
+/*
+ * For pins used as GPIOs, these set which are used as outputs
+ */
+sfr at 0xFD P0DIR;
+sfr at 0xFE P1DIR;
+sfr at 0xFF P2DIR;
+
+sfr at 0x8F P0INP;
+
+/* Select between tri-state and pull up/down
+ * for pins P0_0 - P0_7.
+ */
+#define P0INP_MDP0_7_PULL	(0 << 7)
+#define P0INP_MDP0_7_TRISTATE	(1 << 7)
+#define P0INP_MDP0_6_PULL	(0 << 6)
+#define P0INP_MDP0_6_TRISTATE	(1 << 6)
+#define P0INP_MDP0_5_PULL	(0 << 5)
+#define P0INP_MDP0_5_TRISTATE	(1 << 5)
+#define P0INP_MDP0_4_PULL	(0 << 4)
+#define P0INP_MDP0_4_TRISTATE	(1 << 4)
+#define P0INP_MDP0_3_PULL	(0 << 3)
+#define P0INP_MDP0_3_TRISTATE	(1 << 3)
+#define P0INP_MDP0_2_PULL	(0 << 2)
+#define P0INP_MDP0_2_TRISTATE	(1 << 2)
+#define P0INP_MDP0_1_PULL	(0 << 1)
+#define P0INP_MDP0_1_TRISTATE	(1 << 1)
+#define P0INP_MDP0_0_PULL	(0 << 0)
+#define P0INP_MDP0_0_TRISTATE	(1 << 0)
+
+sfr at 0xF6 P1INP;
+
+/* Select between tri-state and pull up/down
+ * for pins P1_2 - P1_7. Pins P1_0 and P1_1 are
+ * always tri-stated
+ */
+#define P1INP_MDP1_7_PULL	(0 << 7)
+#define P1INP_MDP1_7_TRISTATE	(1 << 7)
+#define P1INP_MDP1_6_PULL	(0 << 6)
+#define P1INP_MDP1_6_TRISTATE	(1 << 6)
+#define P1INP_MDP1_5_PULL	(0 << 5)
+#define P1INP_MDP1_5_TRISTATE	(1 << 5)
+#define P1INP_MDP1_4_PULL	(0 << 4)
+#define P1INP_MDP1_4_TRISTATE	(1 << 4)
+#define P1INP_MDP1_3_PULL	(0 << 3)
+#define P1INP_MDP1_3_TRISTATE	(1 << 3)
+#define P1INP_MDP1_2_PULL	(0 << 2)
+#define P1INP_MDP1_2_TRISTATE	(1 << 2)
+
+sfr at 0xF7 P2INP;
+/* P2INP has three extra bits which are used to choose
+ * between pull-up and pull-down when they are not tri-stated
+ */
+#define P2INP_PDUP2_PULL_UP	(0 << 7)
+#define P2INP_PDUP2_PULL_DOWN	(1 << 7)
+#define P2INP_PDUP1_PULL_UP	(0 << 6)
+#define P2INP_PDUP1_PULL_DOWN	(1 << 6)
+#define P2INP_PDUP0_PULL_UP	(0 << 5)
+#define P2INP_PDUP0_PULL_DOWN	(1 << 5)
+
+/* For the P2 pins, choose between tri-state and pull up/down
+ * mode
+ */
+#define P2INP_MDP2_4_PULL	(0 << 4)
+#define P2INP_MDP2_4_TRISTATE	(1 << 4)
+#define P2INP_MDP2_3_PULL	(0 << 3)
+#define P2INP_MDP2_3_TRISTATE	(1 << 3)
+#define P2INP_MDP2_2_PULL	(0 << 2)
+#define P2INP_MDP2_2_TRISTATE	(1 << 2)
+#define P2INP_MDP2_1_PULL	(0 << 1)
+#define P2INP_MDP2_1_TRISTATE	(1 << 1)
+#define P2INP_MDP2_0_PULL	(0 << 0)
+#define P2INP_MDP2_0_TRISTATE	(1 << 0)
+
+/* GPIO interrupt status flags */
+sfr at 0x89 P0IFG;
+sfr at 0x8A P1IFG;
+sfr at 0x8B P2IFG;
+
+#define P0IFG_USB_RESUME	(1 << 7)
+
+/* GPIO pins */
+sfr at 0x80 P0;
+
+sbit at 0x80 P0_0;
+sbit at 0x81 P0_1;
+sbit at 0x82 P0_2;
+sbit at 0x83 P0_3;
+sbit at 0x84 P0_4;
+sbit at 0x85 P0_5;
+sbit at 0x86 P0_6;
+sbit at 0x87 P0_7;
+
+sfr at 0x90 P1;
+
+sbit at 0x90 P1_0;
+sbit at 0x91 P1_1;
+sbit at 0x92 P1_2;
+sbit at 0x93 P1_3;
+sbit at 0x94 P1_4;
+sbit at 0x95 P1_5;
+sbit at 0x96 P1_6;
+sbit at 0x97 P1_7;
+
+sfr at 0xa0 P2;
+
+sbit at 0xa0 P2_0;
+sbit at 0xa1 P2_1;
+sbit at 0xa2 P2_2;
+sbit at 0xa3 P2_3;
+sbit at 0xa4 P2_4;
+sbit at 0xa5 P2_5;
+sbit at 0xa6 P2_6;
+sbit at 0xa7 P2_7;
+
+/* DMA controller */
+struct cc_dma_channel {
+	uint8_t	src_high;
+	uint8_t	src_low;
+	uint8_t	dst_high;
+	uint8_t	dst_low;
+	uint8_t	len_high;
+	uint8_t	len_low;
+	uint8_t	cfg0;
+	uint8_t	cfg1;
+};
+
+# define DMA_LEN_HIGH_VLEN_MASK		(7 << 5)
+# define DMA_LEN_HIGH_VLEN_LEN		(0 << 5)
+# define DMA_LEN_HIGH_VLEN_PLUS_1	(1 << 5)
+# define DMA_LEN_HIGH_VLEN		(2 << 5)
+# define DMA_LEN_HIGH_VLEN_PLUS_2	(3 << 5)
+# define DMA_LEN_HIGH_VLEN_PLUS_3	(4 << 5)
+# define DMA_LEN_HIGH_MASK		(0x1f)
+
+# define DMA_CFG0_WORDSIZE_8		(0 << 7)
+# define DMA_CFG0_WORDSIZE_16		(1 << 7)
+# define DMA_CFG0_TMODE_MASK		(3 << 5)
+# define DMA_CFG0_TMODE_SINGLE		(0 << 5)
+# define DMA_CFG0_TMODE_BLOCK		(1 << 5)
+# define DMA_CFG0_TMODE_REPEATED_SINGLE	(2 << 5)
+# define DMA_CFG0_TMODE_REPEATED_BLOCK	(3 << 5)
+
+/*
+ * DMA triggers
+ */
+# define DMA_CFG0_TRIGGER_NONE		0
+# define DMA_CFG0_TRIGGER_PREV		1
+# define DMA_CFG0_TRIGGER_T1_CH0	2
+# define DMA_CFG0_TRIGGER_T1_CH1	3
+# define DMA_CFG0_TRIGGER_T1_CH2	4
+# define DMA_CFG0_TRIGGER_T2_OVFL	6
+# define DMA_CFG0_TRIGGER_T3_CH0	7
+# define DMA_CFG0_TRIGGER_T3_CH1	8
+# define DMA_CFG0_TRIGGER_T4_CH0	9
+# define DMA_CFG0_TRIGGER_T4_CH1	10
+# define DMA_CFG0_TRIGGER_IOC_0		12
+# define DMA_CFG0_TRIGGER_IOC_1		13
+# define DMA_CFG0_TRIGGER_URX0		14
+# define DMA_CFG0_TRIGGER_UTX0		15
+# define DMA_CFG0_TRIGGER_URX1		16
+# define DMA_CFG0_TRIGGER_UTX1		17
+# define DMA_CFG0_TRIGGER_FLASH		18
+# define DMA_CFG0_TRIGGER_RADIO		19
+# define DMA_CFG0_TRIGGER_ADC_CHALL	20
+# define DMA_CFG0_TRIGGER_ADC_CH0	21
+# define DMA_CFG0_TRIGGER_ADC_CH1	22
+# define DMA_CFG0_TRIGGER_ADC_CH2	23
+# define DMA_CFG0_TRIGGER_ADC_CH3	24
+# define DMA_CFG0_TRIGGER_ADC_CH4	25
+# define DMA_CFG0_TRIGGER_ADC_CH5	26
+# define DMA_CFG0_TRIGGER_ADC_CH6	27
+# define DMA_CFG0_TRIGGER_I2SRX		27
+# define DMA_CFG0_TRIGGER_ADC_CH7	28
+# define DMA_CFG0_TRIGGER_I2STX		28
+# define DMA_CFG0_TRIGGER_ENC_DW	29
+# define DMA_CFG0_TRIGGER_DNC_UP	30
+
+# define DMA_CFG1_SRCINC_MASK		(3 << 6)
+# define DMA_CFG1_SRCINC_0		(0 << 6)
+# define DMA_CFG1_SRCINC_1		(1 << 6)
+# define DMA_CFG1_SRCINC_2		(2 << 6)
+# define DMA_CFG1_SRCINC_MINUS_1	(3 << 6)
+
+# define DMA_CFG1_DESTINC_MASK		(3 << 4)
+# define DMA_CFG1_DESTINC_0		(0 << 4)
+# define DMA_CFG1_DESTINC_1		(1 << 4)
+# define DMA_CFG1_DESTINC_2		(2 << 4)
+# define DMA_CFG1_DESTINC_MINUS_1	(3 << 4)
+
+# define DMA_CFG1_IRQMASK		(1 << 3)
+# define DMA_CFG1_M8			(1 << 2)
+
+# define DMA_CFG1_PRIORITY_MASK		(3 << 0)
+# define DMA_CFG1_PRIORITY_LOW		(0 << 0)
+# define DMA_CFG1_PRIORITY_NORMAL	(1 << 0)
+# define DMA_CFG1_PRIORITY_HIGH		(2 << 0)
+
+/*
+ * DMAARM - DMA Channel Arm
+ */
+
+sfr at 0xD6 DMAARM;
+
+# define DMAARM_ABORT			(1 << 7)
+# define DMAARM_DMAARM4			(1 << 4)
+# define DMAARM_DMAARM3			(1 << 3)
+# define DMAARM_DMAARM2			(1 << 2)
+# define DMAARM_DMAARM1			(1 << 1)
+# define DMAARM_DMAARM0			(1 << 0)
+
+/*
+ * DMAREQ - DMA Channel Start Request and Status
+ */
+
+sfr at 0xD7 DMAREQ;
+
+# define DMAREQ_DMAREQ4			(1 << 4)
+# define DMAREQ_DMAREQ3			(1 << 3)
+# define DMAREQ_DMAREQ2			(1 << 2)
+# define DMAREQ_DMAREQ1			(1 << 1)
+# define DMAREQ_DMAREQ0			(1 << 0)
+
+/*
+ * DMA configuration 0 address
+ */
+
+sfr at 0xD5 DMA0CFGH;
+sfr at 0xD4 DMA0CFGL;
+
+/*
+ * DMA configuration 1-4 address
+ */
+
+sfr at 0xD3 DMA1CFGH;
+sfr at 0xD2 DMA1CFGL;
+
+/*
+ * DMAIRQ - DMA Interrupt Flag
+ */
+
+sfr at 0xD1 DMAIRQ;
+
+# define DMAIRQ_DMAIF4			(1 << 4)
+# define DMAIRQ_DMAIF3			(1 << 3)
+# define DMAIRQ_DMAIF2			(1 << 2)
+# define DMAIRQ_DMAIF1			(1 << 1)
+# define DMAIRQ_DMAIF0			(1 << 0)
+
+/*
+ * UART registers
+ */
+
+/* USART config/status registers */
+sfr at 0x86 U0CSR;
+sfr at 0xF8 U1CSR;
+
+# define UxCSR_MODE_UART		(1 << 7)
+# define UxCSR_MODE_SPI			(0 << 7)
+# define UxCSR_RE			(1 << 6)
+# define UxCSR_SLAVE			(1 << 5)
+# define UxCSR_MASTER			(0 << 5)
+# define UxCSR_FE			(1 << 4)
+# define UxCSR_ERR			(1 << 3)
+# define UxCSR_RX_BYTE			(1 << 2)
+# define UxCSR_TX_BYTE			(1 << 1)
+# define UxCSR_ACTIVE			(1 << 0)
+
+/* UART configuration registers */
+sfr at 0xc4 U0UCR;
+sfr at 0xfb U1UCR;
+
+# define UxUCR_FLUSH                    (1 << 7)
+# define UxUCR_FLOW_DISABLE             (0 << 6)
+# define UxUCR_FLOW_ENABLE              (1 << 6)
+# define UxUCR_D9_EVEN_PARITY           (0 << 5)
+# define UxUCR_D9_ODD_PARITY            (1 << 5)
+# define UxUCR_BIT9_8_BITS              (0 << 4)
+# define UxUCR_BIT9_9_BITS              (1 << 4)
+# define UxUCR_PARITY_DISABLE           (0 << 3)
+# define UxUCR_PARITY_ENABLE            (1 << 3)
+# define UxUCR_SPB_1_STOP_BIT           (0 << 2)
+# define UxUCR_SPB_2_STOP_BITS          (1 << 2)
+# define UxUCR_STOP_LOW                 (0 << 1)
+# define UxUCR_STOP_HIGH                (1 << 1)
+# define UxUCR_START_LOW                (0 << 0)
+# define UxUCR_START_HIGH               (1 << 0)
+
+/* USART General configuration registers (mostly SPI) */
+sfr at 0xc5 U0GCR;
+sfr at 0xfc U1GCR;
+
+# define UxGCR_CPOL_NEGATIVE		(0 << 7)
+# define UxGCR_CPOL_POSITIVE		(1 << 7)
+# define UxGCR_CPHA_FIRST_EDGE		(0 << 6)
+# define UxGCR_CPHA_SECOND_EDGE		(1 << 6)
+# define UxGCR_ORDER_LSB		(0 << 5)
+# define UxGCR_ORDER_MSB		(1 << 5)
+# define UxGCR_BAUD_E_MASK		(0x1f)
+# define UxGCR_BAUD_E_SHIFT		0
+
+/* USART data registers */
+sfr at 0xc1 U0DBUF;
+__xdata __at (0xDFC1) volatile uint8_t U0DBUFXADDR;
+sfr at 0xf9 U1DBUF;
+__xdata __at (0xDFF9) volatile uint8_t U1DBUFXADDR;
+
+/* USART baud rate registers, M value */
+sfr at 0xc2 U0BAUD;
+sfr at 0xfa U1BAUD;
+
+#endif
diff --git a/check-stack b/check-stack
new file mode 100755
index 00000000..d93e8e44
--- /dev/null
+++ b/check-stack
@@ -0,0 +1,13 @@
+#!/bin/sh
+HEADER=$1
+MEM=$2
+
+HEADER_STACK=`awk '/#define AO_STACK_START/ {print $3}' $HEADER`
+MEM_STACK=`awk '/Stack starts at/ {print $4}' $MEM`
+
+if [ "$HEADER_STACK" != "$MEM_STACK" ]; then
+	echo "Set AO_STACK_START to $MEM_STACK"
+	exit 1
+else
+	exit 0
+fi
author	Keith Packard <keithp@keithp.com>	2009-04-12 20:25:39 -0700
committer	Keith Packard <keithp@keithp.com>	2009-04-12 20:25:39 -0700
commit	1903a86bf2cc6b685ccc475e62eabe49a4ec5b43 (patch)
tree	bc791a4a40f84ea8890e001c2d03afd1abd51d7d